Design of tapered buffers with local interconnect capacitance

This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C/sup 3/RT), is based on maintaining the capacitive load to curre...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1995-02, Vol.30 (2), p.151-155
Hauptverfasser:	Cherkauer, B.S., Friedman, E.G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Capacitance Coupling circuits Degradation Design methodology Driver circuits Electronics Exact sciences and technology Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) Inverters Power dissipation Power system interconnection Propagation delay Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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