CMOS analog MAP decoder for (8,4) Hamming code
Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary compon...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2004-01, Vol.39 (1), p.122-131 |
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| container_end_page | 131 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Winstead, C. Jie Dai Shuhuan Yu Myers, C. Harrison, R.R. Schlegel, C. |
| description | Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s. |
| doi_str_mv | 10.1109/JSSC.2003.820845 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28210535</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1261294</ieee_id><sourcerecordid>2585765301</sourcerecordid><originalsourceid>FETCH-LOGICAL-c351t-ccb006f526ed69a3a2dfdeb4ac0060f5f481eaa9132542aebba36940a935254d3</originalsourceid><addsrcrecordid>eNp9kMtLw0AQxhdRsFbvgpfgwQeYuLOPdPdYglqlpUIVvC2bzaakJE3dbQ7-926IIHjwNMw3v3l9CJ0DTgCwvH9ZrbKEYEwTQbBg_ACNgHMRw4R-HKIRxiBiGerH6MT7TUgZEzBCSbZYriK91XW7jhbT16iwpi2si8rWRTfijt1GM9001XYd9fopOip17e3ZTxyj98eHt2wWz5dPz9l0HhvKYR8bk2OclpyktkilppoUZWFzpk2QccnLsNtqLYESzoi2ea5pKhnWkvKgFHSMroe5O9d-dtbvVVN5Y-tab23beSVkSijQCQTy6l-SCAKYUx7Ayz_gpu1ceNwrSYCGO0gP4QEyrvXe2VLtXNVo96UAq95n1fusep_V4HNouRhaKmvtL05SIJLRb9QNdN4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>921354225</pqid></control><display><type>article</type><title>CMOS analog MAP decoder for (8,4) Hamming code</title><source>IEEE Electronic Library (IEL)</source><creator>Winstead, C. ; Jie Dai ; Shuhuan Yu ; Myers, C. ; Harrison, R.R. ; Schlegel, C.</creator><creatorcontrib>Winstead, C. ; Jie Dai ; Shuhuan Yu ; Myers, C. ; Harrison, R.R. ; Schlegel, C.</creatorcontrib><description>Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2003.820845</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Ambient intelligence ; Analog circuits ; Analog computers ; Bit rate ; Circuit simulation ; Circuit testing ; Circuits ; CMOS ; CMOS process ; Computer simulation ; Decoders ; Design engineering ; Energy consumption ; Hamming codes ; Inversions ; Iterative decoding ; Iterative methods ; Turbo codes</subject><ispartof>IEEE journal of solid-state circuits, 2004-01, Vol.39 (1), p.122-131</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c351t-ccb006f526ed69a3a2dfdeb4ac0060f5f481eaa9132542aebba36940a935254d3</citedby><cites>FETCH-LOGICAL-c351t-ccb006f526ed69a3a2dfdeb4ac0060f5f481eaa9132542aebba36940a935254d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1261294$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1261294$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Winstead, C.</creatorcontrib><creatorcontrib>Jie Dai</creatorcontrib><creatorcontrib>Shuhuan Yu</creatorcontrib><creatorcontrib>Myers, C.</creatorcontrib><creatorcontrib>Harrison, R.R.</creatorcontrib><creatorcontrib>Schlegel, C.</creatorcontrib><title>CMOS analog MAP decoder for (8,4) Hamming code</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s.</description><subject>Ambient intelligence</subject><subject>Analog circuits</subject><subject>Analog computers</subject><subject>Bit rate</subject><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>Computer simulation</subject><subject>Decoders</subject><subject>Design engineering</subject><subject>Energy consumption</subject><subject>Hamming codes</subject><subject>Inversions</subject><subject>Iterative decoding</subject><subject>Iterative methods</subject><subject>Turbo codes</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kMtLw0AQxhdRsFbvgpfgwQeYuLOPdPdYglqlpUIVvC2bzaakJE3dbQ7-926IIHjwNMw3v3l9CJ0DTgCwvH9ZrbKEYEwTQbBg_ACNgHMRw4R-HKIRxiBiGerH6MT7TUgZEzBCSbZYriK91XW7jhbT16iwpi2si8rWRTfijt1GM9001XYd9fopOip17e3ZTxyj98eHt2wWz5dPz9l0HhvKYR8bk2OclpyktkilppoUZWFzpk2QccnLsNtqLYESzoi2ea5pKhnWkvKgFHSMroe5O9d-dtbvVVN5Y-tab23beSVkSijQCQTy6l-SCAKYUx7Ayz_gpu1ceNwrSYCGO0gP4QEyrvXe2VLtXNVo96UAq95n1fusep_V4HNouRhaKmvtL05SIJLRb9QNdN4</recordid><startdate>200401</startdate><enddate>200401</enddate><creator>Winstead, C.</creator><creator>Jie Dai</creator><creator>Shuhuan Yu</creator><creator>Myers, C.</creator><creator>Harrison, R.R.</creator><creator>Schlegel, C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200401</creationdate><title>CMOS analog MAP decoder for (8,4) Hamming code</title><author>Winstead, C. ; Jie Dai ; Shuhuan Yu ; Myers, C. ; Harrison, R.R. ; Schlegel, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c351t-ccb006f526ed69a3a2dfdeb4ac0060f5f481eaa9132542aebba36940a935254d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Ambient intelligence</topic><topic>Analog circuits</topic><topic>Analog computers</topic><topic>Bit rate</topic><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>Computer simulation</topic><topic>Decoders</topic><topic>Design engineering</topic><topic>Energy consumption</topic><topic>Hamming codes</topic><topic>Inversions</topic><topic>Iterative decoding</topic><topic>Iterative methods</topic><topic>Turbo codes</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Winstead, C.</creatorcontrib><creatorcontrib>Jie Dai</creatorcontrib><creatorcontrib>Shuhuan Yu</creatorcontrib><creatorcontrib>Myers, C.</creatorcontrib><creatorcontrib>Harrison, R.R.</creatorcontrib><creatorcontrib>Schlegel, C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Winstead, C.</au><au>Jie Dai</au><au>Shuhuan Yu</au><au>Myers, C.</au><au>Harrison, R.R.</au><au>Schlegel, C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>CMOS analog MAP decoder for (8,4) Hamming code</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2004-01</date><risdate>2004</risdate><volume>39</volume><issue>1</issue><spage>122</spage><epage>131</epage><pages>122-131</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2003.820845</doi><tpages>10</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Ambient intelligence Analog circuits Analog computers Bit rate Circuit simulation Circuit testing Circuits CMOS CMOS process Computer simulation Decoders Design engineering Energy consumption Hamming codes Inversions Iterative decoding Iterative methods Turbo codes |
| title | CMOS analog MAP decoder for (8,4) Hamming code |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T22%3A15%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=CMOS%20analog%20MAP%20decoder%20for%20(8,4)%20Hamming%20code&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Winstead,%20C.&rft.date=2004-01&rft.volume=39&rft.issue=1&rft.spage=122&rft.epage=131&rft.pages=122-131&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2003.820845&rft_dat=%3Cproquest_RIE%3E2585765301%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=921354225&rft_id=info:pmid/&rft_ieee_id=1261294&rfr_iscdi=true |