A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

A 4-Mb CMOS SRAM having 0.2- mu A standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1075-1081
Hauptverfasser:	Sasaki, K., Ishibashi, K., Shimohigashi, K., Yamanaka, T., Moriwake, N., Honjo, S., Ikeda, S., Koike, A., Meguro, S., Minato, O.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit noise CMOS technology Computer architecture Current supplies Decoding Delay effects Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Noise reduction Portable computers Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Voltage
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Zusammenfassung:	A 4-Mb CMOS SRAM having 0.2- mu A standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5- mu m CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 mu m/sup 2/ and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm/sup 2/.< >
ISSN:	0018-9200 1558-173X
DOI:	10.1109/4.62127