3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1994-03, Vol.29 (3), p.298-302
Hauptverfasser:	Murabayashi, F., Hotta, T., Tanaka, S., Yamauchi, T., Yamada, H., Nakano, T., Kobayashi, Y., Bandoh, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Applied sciences BiCMOS integrated circuits Bipolar transistors CMOS technology Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic circuits Low voltage Microprocessors MOSFETs Reduced instruction set computing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Wiring
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