A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity

A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V/sub DD/=2.25 V and T=100/spl deg/C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRA...

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