A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge i...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2001-12, Vol.36 (12), p.1931-1936 |
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| container_end_page | 1936 |
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| container_issue | 12 |
| container_start_page | 1931 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 36 |
| creator | Yang, W. Kelly, D. Mehr, L. Sayuk, M.T. Singer, L. |
| description | This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V. |
| doi_str_mv | 10.1109/4.972143 |
| format | Article |
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The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.972143</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Calibration ; Capacitors ; Circuits ; CMOS ; Dissipation ; Dithering ; Dynamic range ; Energy consumption ; Linearity ; Nonlinearity ; Pipelines ; Power consumption ; Sampling methods ; Signal resolution ; Signal to noise ratio</subject><ispartof>IEEE journal of solid-state circuits, 2001-12, Vol.36 (12), p.1931-1936</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-ac83c9253468b7e4a5387611ead6e3a32731ff23654a836d126fb0d4be728f2d3</citedby><cites>FETCH-LOGICAL-c365t-ac83c9253468b7e4a5387611ead6e3a32731ff23654a836d126fb0d4be728f2d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/972143$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/972143$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yang, W.</creatorcontrib><creatorcontrib>Kelly, D.</creatorcontrib><creatorcontrib>Mehr, L.</creatorcontrib><creatorcontrib>Sayuk, M.T.</creatorcontrib><creatorcontrib>Singer, L.</creatorcontrib><title>A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.</description><subject>Calibration</subject><subject>Capacitors</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Dissipation</subject><subject>Dithering</subject><subject>Dynamic range</subject><subject>Energy consumption</subject><subject>Linearity</subject><subject>Nonlinearity</subject><subject>Pipelines</subject><subject>Power consumption</subject><subject>Sampling methods</subject><subject>Signal resolution</subject><subject>Signal to noise ratio</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0ctLAzEQBvAgCtYqePYUPKiXtJlk8thjba0VWgvW121Jd7O4pc_NLtL_3pUWDx70NAzz44PhI-QceAuAR21sRUYAygPSAKUsAyPfD0mDc7AsEpwfk5MQZvWKaKFBBh0q2SuVyNnijQKyKTWKjYJbrOe-HWh3NJ7QTq9LP_Pyg1rF0ls66feeqCvp43ZT5aGk-XJdlafkKHPz4M_2s0le-nfP3QEbju8fup0hS6RWJXOJlUkklERtp8ajU9IaDeBdqr10UhgJWSZqi85KnYLQ2ZSnOPVG2Eykskmud7nrYrWpfCjjRR4SP5-7pV9VIY4AtbRa2Vpe_SmFBYNG4v9Qa8RIQQ0vf8HZqiqW9btxFGm0aJSo0c0OJcUqhMJn8brIF67YxsDj74pijHcV1fRiR3Pv_Q_bH78ASl6DtQ</recordid><startdate>20011201</startdate><enddate>20011201</enddate><creator>Yang, W.</creator><creator>Kelly, D.</creator><creator>Mehr, L.</creator><creator>Sayuk, M.T.</creator><creator>Singer, L.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>20011201</creationdate><title>A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input</title><author>Yang, W. ; Kelly, D. ; Mehr, L. ; Sayuk, M.T. ; Singer, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c365t-ac83c9253468b7e4a5387611ead6e3a32731ff23654a836d126fb0d4be728f2d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Calibration</topic><topic>Capacitors</topic><topic>Circuits</topic><topic>CMOS</topic><topic>Dissipation</topic><topic>Dithering</topic><topic>Dynamic range</topic><topic>Energy consumption</topic><topic>Linearity</topic><topic>Nonlinearity</topic><topic>Pipelines</topic><topic>Power consumption</topic><topic>Sampling methods</topic><topic>Signal resolution</topic><topic>Signal to noise ratio</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yang, W.</creatorcontrib><creatorcontrib>Kelly, D.</creatorcontrib><creatorcontrib>Mehr, L.</creatorcontrib><creatorcontrib>Sayuk, M.T.</creatorcontrib><creatorcontrib>Singer, L.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yang, W.</au><au>Kelly, D.</au><au>Mehr, L.</au><au>Sayuk, M.T.</au><au>Singer, L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2001-12-01</date><risdate>2001</risdate><volume>36</volume><issue>12</issue><spage>1931</spage><epage>1936</epage><pages>1931-1936</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/4.972143</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2001-12, Vol.36 (12), p.1931-1936 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Calibration Capacitors Circuits CMOS Dissipation Dithering Dynamic range Energy consumption Linearity Nonlinearity Pipelines Power consumption Sampling methods Signal resolution Signal to noise ratio |
| title | A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input |
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