20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems
An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is propos...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1997-01, Vol.32 (1), p.31-37 |
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| container_end_page | 37 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 32 |
| creator | Yamada, H. Tsunotani, M. Kaneyama, F. Seki, S. |
| description | An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s. |
| doi_str_mv | 10.1109/4.553175 |
| format | Article |
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The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.553175</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Asynchronous transfer mode ; Data processing ; Gallium arsenide ; Hardware ; Large scale integration ; Packet switching ; Signal processing ; Switches ; Switching systems ; Throughput</subject><ispartof>IEEE journal of solid-state circuits, 1997-01, Vol.32 (1), p.31-37</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1220-9815c645bd15028136e68178039166d8292896e75dbc03f157255ba81c3bd02d3</citedby><cites>FETCH-LOGICAL-c1220-9815c645bd15028136e68178039166d8292896e75dbc03f157255ba81c3bd02d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/553175$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/553175$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yamada, H.</creatorcontrib><creatorcontrib>Tsunotani, M.</creatorcontrib><creatorcontrib>Kaneyama, F.</creatorcontrib><creatorcontrib>Seki, S.</creatorcontrib><title>20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.</description><subject>Asynchronous transfer mode</subject><subject>Data processing</subject><subject>Gallium arsenide</subject><subject>Hardware</subject><subject>Large scale integration</subject><subject>Packet switching</subject><subject>Signal processing</subject><subject>Switches</subject><subject>Switching systems</subject><subject>Throughput</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><recordid>eNo9kMFLwzAYxYMoOKfg2VNO4qXb9yVNm9wcY87BxIMTvIU2TbXSrTNfi-y_t9rh6fHj_XiHx9g1wgQRzDSeKCUxVSdshErpCFP5dspGAKgjIwDO2QXRZ49xrHHE7gVMNF_mU-LLbEZ8_bLi5OsyCk3XVrt3Tt9V6z542QQ-2zwd8a84UOu3dMnOyqwmf3XMMXt9WGzmj9H6ebmaz9aRQyEgMhqVS2KVF6hAaJSJTzSmGqTBJCm0MEKbxKeqyB3IElUqlMozjU7mBYhCjtntsLsPzVfnqbXbipyv62znm45sv6mMROjFu0F0oSEKvrT7UG2zcLAI9vciG9vhol69GdTKe_-vHcsf7h9cpA</recordid><startdate>199701</startdate><enddate>199701</enddate><creator>Yamada, H.</creator><creator>Tsunotani, M.</creator><creator>Kaneyama, F.</creator><creator>Seki, S.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199701</creationdate><title>20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems</title><author>Yamada, H. ; Tsunotani, M. ; Kaneyama, F. ; Seki, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1220-9815c645bd15028136e68178039166d8292896e75dbc03f157255ba81c3bd02d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Asynchronous transfer mode</topic><topic>Data processing</topic><topic>Gallium arsenide</topic><topic>Hardware</topic><topic>Large scale integration</topic><topic>Packet switching</topic><topic>Signal processing</topic><topic>Switches</topic><topic>Switching systems</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yamada, H.</creatorcontrib><creatorcontrib>Tsunotani, M.</creatorcontrib><creatorcontrib>Kaneyama, F.</creatorcontrib><creatorcontrib>Seki, S.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamada, H.</au><au>Tsunotani, M.</au><au>Kaneyama, F.</au><au>Seki, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1997-01</date><risdate>1997</risdate><volume>32</volume><issue>1</issue><spage>31</spage><epage>37</epage><pages>31-37</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.</abstract><pub>IEEE</pub><doi>10.1109/4.553175</doi><tpages>7</tpages></addata></record> |
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| issn | 0018-9200 1558-173X |
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| source | IEEE Electronic Library (IEL) |
| subjects | Asynchronous transfer mode Data processing Gallium arsenide Hardware Large scale integration Packet switching Signal processing Switches Switching systems Throughput |
| title | 20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems |
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