A 440-ps 64-bit adder in 1.5-V/0.18-mum partially depleted SOI technology

A 440-ps 64-bit adder in 1.5-V/0.18-mum partially depleted SOI technology

A 64-bit adder in 1.5-V/0.18-mum partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-mum partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CM...

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Veröffentlicht in:IEEE journal of solid-state circuits 2001-10, Vol.36 (10), p.1546-1552
Hauptverfasser: Stasiak, D L, Mounes-Toussi, F, Storino, S N
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container_title IEEE journal of solid-state circuits
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creator Stasiak, D L
Mounes-Toussi, F
Storino, S N
description A 64-bit adder in 1.5-V/0.18-mum partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-mum partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits
doi_str_mv 10.1109/4.953483
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title A 440-ps 64-bit adder in 1.5-V/0.18-mum partially depleted SOI technology
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