A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2005-05, Vol.40 (5), p.1119-1129
Hauptverfasser:	Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Park, H.-J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive bandwidth analog voltage-controlled delay line (VCDL) Applied sciences Area measurement Bandwidth Chip formation Chips Circuit properties Circuits of signal characteristics conditioning (including delay circuits) clock synchronization CMOS Delay lines delay-locked loop (DLL) Design. Technologies. Operation analysis. Testing Detectors dual-loop DLL Dynamic link libraries Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency infinite phase shift Integrated circuits Jitter Locks Phase change Phase detection phase detector Phase detectors plesiochronous Power measurement seamless phase change Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Voltage
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