A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO
An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled lo...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1993-09, Vol.28 (9), p.935-940 |
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| container_end_page | 940 |
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| container_issue | 9 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 28 |
| creator | Watanabe, Y. Nakasha, Y. Kato, Y. Odani, K. Abe, M. |
| description | An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s.< > |
| doi_str_mv | 10.1109/4.236172 |
| format | Article |
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To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.236172</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Asynchronous transfer mode ; B-ISDN ; Exact sciences and technology ; FETs ; Frequency ; HEMTs ; Integrated circuit technology ; Large scale integration ; Logic circuits ; Network equipments ; Switches ; Telecommunications ; Telecommunications and information theory ; Teleprocessing networks. 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To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s.< ></description><subject>Applied sciences</subject><subject>Asynchronous transfer mode</subject><subject>B-ISDN</subject><subject>Exact sciences and technology</subject><subject>FETs</subject><subject>Frequency</subject><subject>HEMTs</subject><subject>Integrated circuit technology</subject><subject>Large scale integration</subject><subject>Logic circuits</subject><subject>Network equipments</subject><subject>Switches</subject><subject>Telecommunications</subject><subject>Telecommunications and information theory</subject><subject>Teleprocessing networks. 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Isdn</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Nakasha, Y.</creatorcontrib><creatorcontrib>Kato, Y.</creatorcontrib><creatorcontrib>Odani, K.</creatorcontrib><creatorcontrib>Abe, M.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Watanabe, Y.</au><au>Nakasha, Y.</au><au>Kato, Y.</au><au>Odani, K.</au><au>Abe, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1993-09-01</date><risdate>1993</risdate><volume>28</volume><issue>9</issue><spage>935</spage><epage>940</epage><pages>935-940</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.236172</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1993-09, Vol.28 (9), p.935-940 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28132792 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Asynchronous transfer mode B-ISDN Exact sciences and technology FETs Frequency HEMTs Integrated circuit technology Large scale integration Logic circuits Network equipments Switches Telecommunications Telecommunications and information theory Teleprocessing networks. Isdn Throughput |
| title | A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO |
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