Three-dimensional substrate impedance engineering based on p/sup -//p/sup %2B/ Si substrate for mixed-signal system-on-chip (SoC)

A novel approach for three-dimensional substrate impedance engineering of p/sup -//p/sup / Si substrate is described for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to radio frequency (RF) crosstalk via substrate and on-chip inductor performance. Electroless plating or electro-plating is used to fabricate Faraday cage for crosstalk isolation as well as to provide "true ground" contacts. A self-limiting porous Si (PS) formation process is employed to allow the insertion of PS regions from the backside of the wafer, eliminating completely the waste of chip surface area. On-chip inductors are situated above the semi-insulating PS regions allowing for greatly increased Q-factor and resonance frequency (f/sub r/). RF crosstalk is reduced to the level limited by that across the air gap between the measurement probes.