Design, analysis, and development of novel three-dimensional stacking WLCSP
A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conv...
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| Veröffentlicht in: | IEEE transactions on advanced packaging 2005-08, Vol.28 (3), p.387-396 |
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| container_title | IEEE transactions on advanced packaging |
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| creator | Yuan, C.-A. Cheng Nan Han Ming-Chih Yew Chan-Yen Chou Kou-Ning Chiang |
| description | A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters. |
| doi_str_mv | 10.1109/TADVP.2005.852894 |
| format | Article |
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This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.</description><identifier>ISSN: 1521-3323</identifier><identifier>EISSN: 1557-9980</identifier><identifier>DOI: 10.1109/TADVP.2005.852894</identifier><identifier>CODEN: ITAPFZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Chip scale packaging ; Design engineering ; Design methodology ; Design parameters ; Fabrication ; Factorial analysis ; Finite element method ; Finite element methods ; Mathematical analysis ; Packaging ; Parametric analysis ; Robustness ; Semiconductor device measurement ; Stacking ; Test vehicles ; Testing ; three-dimensional (3-D) stacking ; Vehicles ; Wafer scale integration ; wafer-level packaging</subject><ispartof>IEEE transactions on advanced packaging, 2005-08, Vol.28 (3), p.387-396</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c386t-3abe89ce08b74d1ef74e362eeed3bf0627b1398fd181675faaa2b8cdfda8e83f3</citedby><cites>FETCH-LOGICAL-c386t-3abe89ce08b74d1ef74e362eeed3bf0627b1398fd181675faaa2b8cdfda8e83f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1492507$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1492507$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yuan, C.-A.</creatorcontrib><creatorcontrib>Cheng Nan Han</creatorcontrib><creatorcontrib>Ming-Chih Yew</creatorcontrib><creatorcontrib>Chan-Yen Chou</creatorcontrib><creatorcontrib>Kou-Ning Chiang</creatorcontrib><title>Design, analysis, and development of novel three-dimensional stacking WLCSP</title><title>IEEE transactions on advanced packaging</title><addtitle>TADVP</addtitle><description>A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. 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Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.</description><subject>Chip scale packaging</subject><subject>Design engineering</subject><subject>Design methodology</subject><subject>Design parameters</subject><subject>Fabrication</subject><subject>Factorial analysis</subject><subject>Finite element method</subject><subject>Finite element methods</subject><subject>Mathematical analysis</subject><subject>Packaging</subject><subject>Parametric analysis</subject><subject>Robustness</subject><subject>Semiconductor device measurement</subject><subject>Stacking</subject><subject>Test vehicles</subject><subject>Testing</subject><subject>three-dimensional (3-D) stacking</subject><subject>Vehicles</subject><subject>Wafer scale integration</subject><subject>wafer-level packaging</subject><issn>1521-3323</issn><issn>1557-9980</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkU1Lw0AQhoMoWKs_QLwED3oxdT-ym91jaf3CggWrHpdNdramptmaTYX-ezdWEDzoad4ZnpmB942iY4wGGCN5ORuOn6cDghAbCEaETHeiHmYsS6QUaLfTBCeUErofHXi_QAinIiW96H4MvpzXF7GudbXxpe-UiQ18QOVWS6jb2Nm4dqGN29cGIDFlmPrSBT72rS7eynoev0xGj9PDaM_qysPRd-1HT9dXs9FtMnm4uRsNJ0lBBW8TqnMQsgAk8iw1GGyWAuUEAAzNLeIkyzGVwhosMM-Y1VqTXBTGGi1AUEv70fn27qpx72vwrVqWvoCq0jW4tVdCckJSwUQgz_4kiSSYpxz_DwoU3EQdePoLXLh1E7wIb7nEiHPWQXgLFY3zvgGrVk251M1GYaS6uNRXXKqLS23jCjsn250yGPHDp5IwlNFP1D-Qwg</recordid><startdate>20050801</startdate><enddate>20050801</enddate><creator>Yuan, C.-A.</creator><creator>Cheng Nan Han</creator><creator>Ming-Chih Yew</creator><creator>Chan-Yen Chou</creator><creator>Kou-Ning Chiang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TADVP.2005.852894</doi><tpages>10</tpages></addata></record> |
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| ispartof | IEEE transactions on advanced packaging, 2005-08, Vol.28 (3), p.387-396 |
| issn | 1521-3323 1557-9980 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Chip scale packaging Design engineering Design methodology Design parameters Fabrication Factorial analysis Finite element method Finite element methods Mathematical analysis Packaging Parametric analysis Robustness Semiconductor device measurement Stacking Test vehicles Testing three-dimensional (3-D) stacking Vehicles Wafer scale integration wafer-level packaging |
| title | Design, analysis, and development of novel three-dimensional stacking WLCSP |
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