A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit
A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VC...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-04, Vol.53 (4), p.842-847 |
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| container_title | IEEE transactions on circuits and systems. 1, Fundamental theory and applications |
| container_volume | 53 |
| creator | Yang, Rong-Jyi Chao, Kuan-Hua Liu, Shen-Iuan |
| description | A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps. |
| doi_str_mv | 10.1109/TCSI.2005.862071 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_27997506</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1618871</ieee_id><sourcerecordid>27997506</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1396-9b62901d07a62c58f03fc9fab24142a5e6903d94a437b214140d6ccda490bd033</originalsourceid><addsrcrecordid>eNpFkM9LwzAUx4MoOKd3wUtP3rK9JG2aHMfQOZh4cJ5DmqQQ7dqatML-e1MqeHq_vt_3Hh-E7gmsCAG5Pm7f9ysKUKwEp1CSC7QgRSEwCOCXU55LLBgV1-gmxk8AKoGRBdpvsmTCr1Uf17FvsuhPa4p3qcxM1w6-Hbsx4qAHl5mmM19YtxZbPWgcnOl-XDhnxgcz-uEWXdW6ie7uLy7Rx_PTcfuCD2-7_XZzwIYwybGseDpNLJSaU1OIGlhtZK0rmpOc6sLx9JiVuc5ZWVGSmmC5MVbnEioLjC3R47y3D9336OKgTj4a1zS6delXRUspywJ4EsIsNKGLMbha9cGfdDgrAmpipiZmamKmZmbJ8jBbvHPuX86JEGn6C5C-Zhg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27997506</pqid></control><display><type>article</type><title>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit</title><source>IEEE Electronic Library (IEL)</source><creator>Yang, Rong-Jyi ; Chao, Kuan-Hua ; Liu, Shen-Iuan</creator><creatorcontrib>Yang, Rong-Jyi ; Chao, Kuan-Hua ; Liu, Shen-Iuan</creatorcontrib><description>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.</description><identifier>ISSN: 1549-8328</identifier><identifier>ISSN: 1057-7122</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2005.862071</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bit rate ; Circuits ; Clock-and-data-recovery (CDR) ; Clocks ; continuous rate ; Detectors ; Digital control ; Frequency ; frequency detector ; Jitter ; Phase detection ; Voltage control ; voltage-controlled oscillator (VCO) ; Voltage-controlled oscillators</subject><ispartof>IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-04, Vol.53 (4), p.842-847</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1396-9b62901d07a62c58f03fc9fab24142a5e6903d94a437b214140d6ccda490bd033</citedby><cites>FETCH-LOGICAL-c1396-9b62901d07a62c58f03fc9fab24142a5e6903d94a437b214140d6ccda490bd033</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1618871$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1618871$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yang, Rong-Jyi</creatorcontrib><creatorcontrib>Chao, Kuan-Hua</creatorcontrib><creatorcontrib>Liu, Shen-Iuan</creatorcontrib><title>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit</title><title>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</title><addtitle>TCSI</addtitle><description>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.</description><subject>Bit rate</subject><subject>Circuits</subject><subject>Clock-and-data-recovery (CDR)</subject><subject>Clocks</subject><subject>continuous rate</subject><subject>Detectors</subject><subject>Digital control</subject><subject>Frequency</subject><subject>frequency detector</subject><subject>Jitter</subject><subject>Phase detection</subject><subject>Voltage control</subject><subject>voltage-controlled oscillator (VCO)</subject><subject>Voltage-controlled oscillators</subject><issn>1549-8328</issn><issn>1057-7122</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpFkM9LwzAUx4MoOKd3wUtP3rK9JG2aHMfQOZh4cJ5DmqQQ7dqatML-e1MqeHq_vt_3Hh-E7gmsCAG5Pm7f9ysKUKwEp1CSC7QgRSEwCOCXU55LLBgV1-gmxk8AKoGRBdpvsmTCr1Uf17FvsuhPa4p3qcxM1w6-Hbsx4qAHl5mmM19YtxZbPWgcnOl-XDhnxgcz-uEWXdW6ie7uLy7Rx_PTcfuCD2-7_XZzwIYwybGseDpNLJSaU1OIGlhtZK0rmpOc6sLx9JiVuc5ZWVGSmmC5MVbnEioLjC3R47y3D9336OKgTj4a1zS6delXRUspywJ4EsIsNKGLMbha9cGfdDgrAmpipiZmamKmZmbJ8jBbvHPuX86JEGn6C5C-Zhg</recordid><startdate>200604</startdate><enddate>200604</enddate><creator>Yang, Rong-Jyi</creator><creator>Chao, Kuan-Hua</creator><creator>Liu, Shen-Iuan</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>200604</creationdate><title>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit</title><author>Yang, Rong-Jyi ; Chao, Kuan-Hua ; Liu, Shen-Iuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1396-9b62901d07a62c58f03fc9fab24142a5e6903d94a437b214140d6ccda490bd033</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Bit rate</topic><topic>Circuits</topic><topic>Clock-and-data-recovery (CDR)</topic><topic>Clocks</topic><topic>continuous rate</topic><topic>Detectors</topic><topic>Digital control</topic><topic>Frequency</topic><topic>frequency detector</topic><topic>Jitter</topic><topic>Phase detection</topic><topic>Voltage control</topic><topic>voltage-controlled oscillator (VCO)</topic><topic>Voltage-controlled oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yang, Rong-Jyi</creatorcontrib><creatorcontrib>Chao, Kuan-Hua</creatorcontrib><creatorcontrib>Liu, Shen-Iuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yang, Rong-Jyi</au><au>Chao, Kuan-Hua</au><au>Liu, Shen-Iuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit</atitle><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle><stitle>TCSI</stitle><date>2006-04</date><risdate>2006</risdate><volume>53</volume><issue>4</issue><spage>842</spage><epage>847</epage><pages>842-847</pages><issn>1549-8328</issn><issn>1057-7122</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.</abstract><pub>IEEE</pub><doi>10.1109/TCSI.2005.862071</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-04, Vol.53 (4), p.842-847 |
| issn | 1549-8328 1057-7122 1558-0806 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_27997506 |
| source | IEEE Electronic Library (IEL) |
| subjects | Bit rate Circuits Clock-and-data-recovery (CDR) Clocks continuous rate Detectors Digital control Frequency frequency detector Jitter Phase detection Voltage control voltage-controlled oscillator (VCO) Voltage-controlled oscillators |
| title | A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T11%3A26%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20200-Mbps/spl%20sim/2-Gbps%20continuous-rate%20clock-and-data-recovery%20circuit&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%201,%20Fundamental%20theory%20and%20applications&rft.au=Yang,%20Rong-Jyi&rft.date=2006-04&rft.volume=53&rft.issue=4&rft.spage=842&rft.epage=847&rft.pages=842-847&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2005.862071&rft_dat=%3Cproquest_RIE%3E27997506%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27997506&rft_id=info:pmid/&rft_ieee_id=1618871&rfr_iscdi=true |