Design of an efficient FFT Processor for OFDM systems
Orthogonal frequency division multiplexing (OFDM) system is famous for its robustness against frequency selective fading channel and the FFT processor is the critical block in all OFDM systems. In this article, an efficient FFT processor architecture suitable for OFDM systems is proposed. In order t...
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| Veröffentlicht in: | IEEE transactions on consumer electronics 2005-11, Vol.51 (4), p.1099-1103 |
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| container_title | IEEE transactions on consumer electronics |
| container_volume | 51 |
| creator | Haining Jiang, Haining Jiang Hanwen Luo, Hanwen Luo Jifeng Tian, Jifeng Tian Wentao Song, Wentao Song |
| description | Orthogonal frequency division multiplexing (OFDM) system is famous for its robustness against frequency selective fading channel and the FFT processor is the critical block in all OFDM systems. In this article, an efficient FFT processor architecture suitable for OFDM systems is proposed. In order to meet the requirements of high-speed data transmission and low-area consumption in OFDM systems, two novel butterfly algorithms - "parallel butterfly algorithm " and "dual butterfly algorithm" - are developed in the design of butterfly unit, which is the kernel in FFT processor. The FFT processor with these butterfly algorithms has high throughput and requires relatively small areas. Performance evaluation demonstrates that the proposed FFT architecture can meet the requirement of wireless LAN (IEEE 802.11a) standard. |
| doi_str_mv | 10.1109/TCE.2005.1561830 |
| format | Article |
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In this article, an efficient FFT processor architecture suitable for OFDM systems is proposed. In order to meet the requirements of high-speed data transmission and low-area consumption in OFDM systems, two novel butterfly algorithms - "parallel butterfly algorithm " and "dual butterfly algorithm" - are developed in the design of butterfly unit, which is the kernel in FFT processor. The FFT processor with these butterfly algorithms has high throughput and requires relatively small areas. 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In this article, an efficient FFT processor architecture suitable for OFDM systems is proposed. In order to meet the requirements of high-speed data transmission and low-area consumption in OFDM systems, two novel butterfly algorithms - "parallel butterfly algorithm " and "dual butterfly algorithm" - are developed in the design of butterfly unit, which is the kernel in FFT processor. The FFT processor with these butterfly algorithms has high throughput and requires relatively small areas. Performance evaluation demonstrates that the proposed FFT architecture can meet the requirement of wireless LAN (IEEE 802.11a) standard.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCE.2005.1561830</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Architecture Butterflies Clocks Data communication Design engineering Digital video broadcasting Hardware High speed Microprocessors OFDM modulation Orthogonal Frequency Division Multiplexing Parallel architectures Pipelines Robustness Throughput Wireless LAN |
| title | Design of an efficient FFT Processor for OFDM systems |
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