CDF level 2 trigger upgrade
We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older...
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Veröffentlicht in: | IEEE transactions on nuclear science 2006-04, Vol.53 (2), p.653-658 |
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creator | Anikeev, K. Bogdan, M. Demaat, R. Fedorko, W. Frisch, H. Hahn, K. Hakala, M. Keener, P. Kim, Y. Kroll, J. Kwang, S. Lewis, J. Lin, C. Liu, T. Marjamaa, F. Mansikkala, T. Neu, C. Pitkanen, S. Reisert, B. Rusu, V. Sanders, H. Shochet, M. Stabenau, H. Van Berg, R. Wilson, P. Whiteson, D. Wittich, P. |
description | We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system. |
doi_str_mv | 10.1109/TNS.2006.871782 |
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The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2006.871782</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bandwidth ; Commissioning ; Computer buffers ; Data links ; Detectors ; Field programmable gate arrays ; FPGA based hardware ; Hardware ; Instruments ; Mezzanines ; Phase detection ; Physics ; Pulsars ; real-time systems ; Robustness ; Running ; Springs ; trigger ; Upstream</subject><ispartof>IEEE transactions on nuclear science, 2006-04, Vol.53 (2), p.653-658</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c393t-cb2c4836ea0e3c44f1ab2bf09b4cb6b9cbf2858ab3e29196e5ba3893c42af28d3</citedby><cites>FETCH-LOGICAL-c393t-cb2c4836ea0e3c44f1ab2bf09b4cb6b9cbf2858ab3e29196e5ba3893c42af28d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1621380$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1621380$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Anikeev, K.</creatorcontrib><creatorcontrib>Bogdan, M.</creatorcontrib><creatorcontrib>Demaat, R.</creatorcontrib><creatorcontrib>Fedorko, W.</creatorcontrib><creatorcontrib>Frisch, H.</creatorcontrib><creatorcontrib>Hahn, K.</creatorcontrib><creatorcontrib>Hakala, M.</creatorcontrib><creatorcontrib>Keener, P.</creatorcontrib><creatorcontrib>Kim, Y.</creatorcontrib><creatorcontrib>Kroll, J.</creatorcontrib><creatorcontrib>Kwang, S.</creatorcontrib><creatorcontrib>Lewis, J.</creatorcontrib><creatorcontrib>Lin, C.</creatorcontrib><creatorcontrib>Liu, T.</creatorcontrib><creatorcontrib>Marjamaa, F.</creatorcontrib><creatorcontrib>Mansikkala, T.</creatorcontrib><creatorcontrib>Neu, C.</creatorcontrib><creatorcontrib>Pitkanen, S.</creatorcontrib><creatorcontrib>Reisert, B.</creatorcontrib><creatorcontrib>Rusu, V.</creatorcontrib><creatorcontrib>Sanders, H.</creatorcontrib><creatorcontrib>Shochet, M.</creatorcontrib><creatorcontrib>Stabenau, H.</creatorcontrib><creatorcontrib>Van Berg, R.</creatorcontrib><creatorcontrib>Wilson, P.</creatorcontrib><creatorcontrib>Whiteson, D.</creatorcontrib><creatorcontrib>Wittich, P.</creatorcontrib><title>CDF level 2 trigger upgrade</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.</description><subject>Bandwidth</subject><subject>Commissioning</subject><subject>Computer buffers</subject><subject>Data links</subject><subject>Detectors</subject><subject>Field programmable gate arrays</subject><subject>FPGA based hardware</subject><subject>Hardware</subject><subject>Instruments</subject><subject>Mezzanines</subject><subject>Phase detection</subject><subject>Physics</subject><subject>Pulsars</subject><subject>real-time systems</subject><subject>Robustness</subject><subject>Running</subject><subject>Springs</subject><subject>trigger</subject><subject>Upstream</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp90DtLA0EQB_BFFIyP2iLNYSE2l-z7dkqJRoWghbFedjdz4cLl4W5O8Nu74QTBwmoY5jcD8yfkitERYxTG85e3EadUj0zFKsOPyIApZUqmKnNMBpQyU4IEOCVnKa1yKxVVAzKc3E-LFj-xLXixj81yibHodsvoFnhBTmrXJrz8qefkffownzyVs9fH58ndrAwCxL4MngdphEZHUQQpa-Y89zUFL4PXHoKvuVHGeYEcGGhU3gkDmXKXJwtxTm76u7u4_egw7e26SQHb1m1w2yXLKwAqtc7w9l_IdMU4cC5pptd_6GrbxU1-wwLjFKjSVUbjHoW4TSlibXexWbv4ZRm1h1BtDtUeQrV9qHlj2G80iPirNWfCUPENqp1vvA</recordid><startdate>20060401</startdate><enddate>20060401</enddate><creator>Anikeev, K.</creator><creator>Bogdan, M.</creator><creator>Demaat, R.</creator><creator>Fedorko, W.</creator><creator>Frisch, H.</creator><creator>Hahn, K.</creator><creator>Hakala, M.</creator><creator>Keener, P.</creator><creator>Kim, Y.</creator><creator>Kroll, J.</creator><creator>Kwang, S.</creator><creator>Lewis, J.</creator><creator>Lin, C.</creator><creator>Liu, T.</creator><creator>Marjamaa, F.</creator><creator>Mansikkala, T.</creator><creator>Neu, C.</creator><creator>Pitkanen, S.</creator><creator>Reisert, B.</creator><creator>Rusu, V.</creator><creator>Sanders, H.</creator><creator>Shochet, M.</creator><creator>Stabenau, H.</creator><creator>Van Berg, R.</creator><creator>Wilson, P.</creator><creator>Whiteson, D.</creator><creator>Wittich, P.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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science</jtitle><stitle>TNS</stitle><date>2006-04-01</date><risdate>2006</risdate><volume>53</volume><issue>2</issue><spage>653</spage><epage>658</epage><pages>653-658</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2006.871782</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Bandwidth Commissioning Computer buffers Data links Detectors Field programmable gate arrays FPGA based hardware Hardware Instruments Mezzanines Phase detection Physics Pulsars real-time systems Robustness Running Springs trigger Upstream |
title | CDF level 2 trigger upgrade |
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