A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS
A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2005-12, Vol.40 (12), p.2416-2427 |
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| container_end_page | 2427 |
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| container_issue | 12 |
| container_start_page | 2416 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 40 |
| creator | Dorrer, L. Kuttner, F. Greco, P. Torta, P. Hartig, T. |
| description | A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/. |
| doi_str_mv | 10.1109/JSSC.2005.856282 |
| format | Article |
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It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.</description><subject>3G mobile communication</subject><subject>Bandwidth</subject><subject>Capacitive feedforward filter design</subject><subject>Clocks</subject><subject>CMOS process</subject><subject>continuous-time delta-sigma ADC</subject><subject>digital receiver</subject><subject>dynamic element matching</subject><subject>Energy consumption</subject><subject>Finite impulse response filter</subject><subject>Interpolation</subject><subject>Jitter</subject><subject>jitter tolerant</subject><subject>low power</subject><subject>multibit delta-sigma ADC</subject><subject>scrambling</subject><subject>Signal resolution</subject><subject>Stability</subject><subject>tracking ADC</subject><subject>UMTS</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpFkElPwzAQhS0EEqVwR-LiEze33uI4xxKWgiiVCAhuluM4xTRLGydC9NeTEiROo5l5b_TmA-Cc4AkhOJo-JEk8oRgHExkIKukBGJEgkIiE7P0QjDAmEkX9_hiceP_Zt5xLMgLrGWSofIMhR9kVTJ6eIUWL-Q6aumpd1dWdR60rLcxs0Wrk3arUcHYdwy_XfkAN20abtatWv7Ntp3vTzjbQVbCPxdDUbwpYdtMSxotlcgqOcl14e_ZXx-D19uYlnqPH5d19PHtEhrBIIh4GhuU2D5jAYaojYYNUGIHTkMvQRMZKwzRlWZpHlBOhLWOZESI3Wa5zTAQbg8vh7qapt531rSqdN7YodGX7hxQNo5ATKnshHoSmqb1vbK42jSt1860IVnuqak9V7amqgWpvuRgszlr7Lw-4oESyHyyMb-w</recordid><startdate>200512</startdate><enddate>200512</enddate><creator>Dorrer, L.</creator><creator>Kuttner, F.</creator><creator>Greco, P.</creator><creator>Torta, P.</creator><creator>Hartig, T.</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>200512</creationdate><title>A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS</title><author>Dorrer, L. ; Kuttner, F. ; Greco, P. ; Torta, P. ; Hartig, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1398-475c3fef53607ba96e5b6c60b7487c9ce8c3a23dbf92416ae33dc66fcdfaf0163</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><topic>3G mobile communication</topic><topic>Bandwidth</topic><topic>Capacitive feedforward filter design</topic><topic>Clocks</topic><topic>CMOS process</topic><topic>continuous-time delta-sigma ADC</topic><topic>digital receiver</topic><topic>dynamic element matching</topic><topic>Energy consumption</topic><topic>Finite impulse response filter</topic><topic>Interpolation</topic><topic>Jitter</topic><topic>jitter tolerant</topic><topic>low power</topic><topic>multibit delta-sigma ADC</topic><topic>scrambling</topic><topic>Signal resolution</topic><topic>Stability</topic><topic>tracking ADC</topic><topic>UMTS</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Dorrer, L.</creatorcontrib><creatorcontrib>Kuttner, F.</creatorcontrib><creatorcontrib>Greco, P.</creatorcontrib><creatorcontrib>Torta, P.</creatorcontrib><creatorcontrib>Hartig, T.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE/IET Electronic Library</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dorrer, L.</au><au>Kuttner, F.</au><au>Greco, P.</au><au>Torta, P.</au><au>Hartig, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2005-12</date><risdate>2005</risdate><volume>40</volume><issue>12</issue><spage>2416</spage><epage>2427</epage><pages>2416-2427</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.2005.856282</doi><tpages>12</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2416-2427 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_27974128 |
| source | IEEE/IET Electronic Library |
| subjects | 3G mobile communication Bandwidth Capacitive feedforward filter design Clocks CMOS process continuous-time delta-sigma ADC digital receiver dynamic element matching Energy consumption Finite impulse response filter Interpolation Jitter jitter tolerant low power multibit delta-sigma ADC scrambling Signal resolution Stability tracking ADC UMTS |
| title | A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS |
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