Hardware‐Software Implementation of MPEG‐4 Video Codec
This paper presents an MPEG‐4 video codec, called MoVa, for video coding applications that adopts 3G‐324M. We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational r...
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| Veröffentlicht in: | ETRI journal 2003-12, Vol.25 (6), p.489-502 |
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| creator | Kim, Seong‐Min Park, Ju‐Hyun Park, Seong‐Mo Koo, Bon‐Tae Shin, Kyoung‐Seon Suh, Ki‐Bum Kim, Ig‐Kyun Eum, Nak‐Woong Kim, Kyung‐Soo |
| description | This paper presents an MPEG‐4 video codec, called MoVa, for video coding applications that adopts 3G‐324M. We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG‐4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment. |
| doi_str_mv | 10.4218/etrij.03.0102.0019 |
| format | Article |
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We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG‐4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.</description><identifier>ISSN: 1225-6463</identifier><identifier>EISSN: 2233-7326</identifier><identifier>DOI: 10.4218/etrij.03.0102.0019</identifier><language>eng</language><publisher>Taejon: Electronics and Telecommunications Research Institute</publisher><subject>3G‐324M ; Applied sciences ; ARM7TDMI ; Artificial intelligence ; Coding, codes ; Computer science; control theory; systems ; Electronics ; Exact sciences and technology ; Image processing ; Information, signal and communications theory ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; MoVa ; MPEG‐4 ; Pattern recognition. Digital image processing. Computational geometry ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal and communications theory ; Signal processing ; Telecommunications and information theory</subject><ispartof>ETRI journal, 2003-12, Vol.25 (6), p.489-502</ispartof><rights>2003 ETRI</rights><rights>2004 INIST-CNRS</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c3999-e96ba751a562467aa04fa7820634c0e3d668a61dcb7c9bda54495e2cd2cb33093</citedby><cites>FETCH-LOGICAL-c3999-e96ba751a562467aa04fa7820634c0e3d668a61dcb7c9bda54495e2cd2cb33093</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.4218%2Fetrij.03.0102.0019$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.4218%2Fetrij.03.0102.0019$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,776,780,1427,27901,27902,46384,46808</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=15341936$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kim, Seong‐Min</creatorcontrib><creatorcontrib>Park, Ju‐Hyun</creatorcontrib><creatorcontrib>Park, Seong‐Mo</creatorcontrib><creatorcontrib>Koo, Bon‐Tae</creatorcontrib><creatorcontrib>Shin, Kyoung‐Seon</creatorcontrib><creatorcontrib>Suh, Ki‐Bum</creatorcontrib><creatorcontrib>Kim, Ig‐Kyun</creatorcontrib><creatorcontrib>Eum, Nak‐Woong</creatorcontrib><creatorcontrib>Kim, Kyung‐Soo</creatorcontrib><title>Hardware‐Software Implementation of MPEG‐4 Video Codec</title><title>ETRI journal</title><description>This paper presents an MPEG‐4 video codec, called MoVa, for video coding applications that adopts 3G‐324M. We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG‐4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.</description><subject>3G‐324M</subject><subject>Applied sciences</subject><subject>ARM7TDMI</subject><subject>Artificial intelligence</subject><subject>Coding, codes</subject><subject>Computer science; control theory; systems</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Image processing</subject><subject>Information, signal and communications theory</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>MoVa</subject><subject>MPEG‐4</subject><subject>Pattern recognition. Digital image processing. Computational geometry</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal and communications theory</subject><subject>Signal processing</subject><subject>Telecommunications and information theory</subject><issn>1225-6463</issn><issn>2233-7326</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><recordid>eNqNkL1OwzAURi0EEqXwAkxZYEu4_okTs6GqtJWKQFBYrRvHkVLlp9ipqm48As_Ik5BQJFame4fzneEQckkhEoymN7Zz5ToCHgEFFgFQdURGjHEeJpzJYzKijMWhFJKfkjPv1wAMRJyOyO0cXb5DZ78-Pl_aohveYFFvKlvbpsOubJugLYKHp-msJ0TwVua2DSZtbs05OSmw8vbi947J6_10NZmHy8fZYnK3DA1XSoVWyQyTmGIsmZAJIogCk5SB5MKA5bmUKUqamywxKssxFkLFlpmcmYxzUHxMrg_ejWvft9Z3ui69sVWFjW23XrNEgZCU9iA7gMa13jtb6I0ra3R7TUEPmfRPJg1cD5n0kKkfXf3a0RusCoeNKf3fMuaip2TPpQduV1Z2_w-znq6e-8ip4t9F3nrh</recordid><startdate>200312</startdate><enddate>200312</enddate><creator>Kim, Seong‐Min</creator><creator>Park, Ju‐Hyun</creator><creator>Park, Seong‐Mo</creator><creator>Koo, Bon‐Tae</creator><creator>Shin, Kyoung‐Seon</creator><creator>Suh, Ki‐Bum</creator><creator>Kim, Ig‐Kyun</creator><creator>Eum, Nak‐Woong</creator><creator>Kim, Kyung‐Soo</creator><general>Electronics and Telecommunications Research Institute</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>200312</creationdate><title>Hardware‐Software Implementation of MPEG‐4 Video Codec</title><author>Kim, Seong‐Min ; Park, Ju‐Hyun ; Park, Seong‐Mo ; Koo, Bon‐Tae ; Shin, Kyoung‐Seon ; Suh, Ki‐Bum ; Kim, Ig‐Kyun ; Eum, Nak‐Woong ; Kim, Kyung‐Soo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3999-e96ba751a562467aa04fa7820634c0e3d668a61dcb7c9bda54495e2cd2cb33093</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>3G‐324M</topic><topic>Applied sciences</topic><topic>ARM7TDMI</topic><topic>Artificial intelligence</topic><topic>Coding, codes</topic><topic>Computer science; control theory; systems</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Image processing</topic><topic>Information, signal and communications theory</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>MoVa</topic><topic>MPEG‐4</topic><topic>Pattern recognition. Digital image processing. Computational geometry</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal and communications theory</topic><topic>Signal processing</topic><topic>Telecommunications and information theory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kim, Seong‐Min</creatorcontrib><creatorcontrib>Park, Ju‐Hyun</creatorcontrib><creatorcontrib>Park, Seong‐Mo</creatorcontrib><creatorcontrib>Koo, Bon‐Tae</creatorcontrib><creatorcontrib>Shin, Kyoung‐Seon</creatorcontrib><creatorcontrib>Suh, Ki‐Bum</creatorcontrib><creatorcontrib>Kim, Ig‐Kyun</creatorcontrib><creatorcontrib>Eum, Nak‐Woong</creatorcontrib><creatorcontrib>Kim, Kyung‐Soo</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>ETRI journal</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kim, Seong‐Min</au><au>Park, Ju‐Hyun</au><au>Park, Seong‐Mo</au><au>Koo, Bon‐Tae</au><au>Shin, Kyoung‐Seon</au><au>Suh, Ki‐Bum</au><au>Kim, Ig‐Kyun</au><au>Eum, Nak‐Woong</au><au>Kim, Kyung‐Soo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hardware‐Software Implementation of MPEG‐4 Video Codec</atitle><jtitle>ETRI journal</jtitle><date>2003-12</date><risdate>2003</risdate><volume>25</volume><issue>6</issue><spage>489</spage><epage>502</epage><pages>489-502</pages><issn>1225-6463</issn><eissn>2233-7326</eissn><abstract>This paper presents an MPEG‐4 video codec, called MoVa, for video coding applications that adopts 3G‐324M. We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG‐4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. 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| subjects | 3G‐324M Applied sciences ARM7TDMI Artificial intelligence Coding, codes Computer science control theory systems Electronics Exact sciences and technology Image processing Information, signal and communications theory Integrated circuits Integrated circuits by function (including memories and processors) MoVa MPEG‐4 Pattern recognition. Digital image processing. Computational geometry Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal processing Telecommunications and information theory |
| title | Hardware‐Software Implementation of MPEG‐4 Video Codec |
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