Thorough characterization of deep-submicron surface and buried channel pMOSFETs

In this paper, the short channel effects in buried and surface channel pMOSFETs are studied. The effective channel length, threshold voltage, source–drain series resistance, carrier mobility in various temperature ranges and the drain-induced-barrier-lowering effect are investigated. Hot carrier degradation is performed in order to extrapolate the device lifetimes and the maximum drain bias that can be applied. Low frequency noise measurements are also carried out in order to evaluate the impact of the gate doping type on the device noise performance.