Reconfigurable Architectures for System Level Applications of Adaptive Computing
The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a high-speed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created...
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| Veröffentlicht in: | VLSI Design 2000-01, Vol.2000 (3), p.c265-279 |
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| container_title | VLSI Design |
| container_volume | 2000 |
| creator | Schott, Brian Crago, Stephen P Parker, Robert H Chen, Chen H Carter, Lauretta C Czarnaski, Joseph P French, Matthew Hom, Ivan Tho, Tam Valenti, Terri |
| description | The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a high-speed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created. The Research Reference Platform (RRP) is a Myrinet^(TM) cluster of PCs with PCI-based FPGA accelerators (SLAAC-1). The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPC^(TM) nodes with VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad- PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for successful ACS technology insertions is source-code compatibility between the RRP and DRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2 accelerators and how the network-centric SLAAC system-level architecture has shaped their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR) algorithm to SLAAC-2 is also discussed. |
| doi_str_mv | 10.1155/2000/28323 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_airit</sourceid><recordid>TN_cdi_proquest_miscellaneous_27669560</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><airiti_id>P20151222006_200012_201612130021_201612130021_c265_279</airiti_id><sourcerecordid>27669560</sourcerecordid><originalsourceid>FETCH-LOGICAL-a331t-a41cf4cb512fc2cfcf5298685ff1cda2d8b4b29afce08a810269b992ee1249f53</originalsourceid><addsrcrecordid>eNpVkE1LxDAYhHNQcF29-Aty8lbN-7aJzbEsfsGKix_graTZN2uWblObdMF_b2W9eBoGHmaGYewCxBWAlNcohLjGMsf8iM1AKJlJKD5O2GmMWyGgmKAZW72QDZ3zm3EwTUu8GuynT2TTOFDkLgz89Tsm2vEl7anlVd-33prkQxd5cLxamz75PfFF2PVj8t3mjB0700Y6_9M5e7-7fVs8ZMvn-8dFtcxMnkPKTAHWFbaRgM6iddZJ1KUqpXNg1wbXZVM0qI2zJEpTgkClG62RCLDQTuZzdnnI7YfwNVJM9c5HS21rOgpjrPFGKS2VmMCnA2j84JOvt2EcumlZvUIBUz1OP6n69yzASUABQi4Ewn9jUckpVOc_i0dlVg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27669560</pqid></control><display><type>article</type><title>Reconfigurable Architectures for System Level Applications of Adaptive Computing</title><source>Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals</source><source>Wiley-Blackwell Open Access Titles</source><source>Alma/SFX Local Collection</source><creator>Schott, Brian ; Crago, Stephen P ; Parker, Robert H ; Chen, Chen H ; Carter, Lauretta C ; Czarnaski, Joseph P ; French, Matthew ; Hom, Ivan ; Tho, Tam ; Valenti, Terri</creator><creatorcontrib>Schott, Brian ; Crago, Stephen P ; Parker, Robert H ; Chen, Chen H ; Carter, Lauretta C ; Czarnaski, Joseph P ; French, Matthew ; Hom, Ivan ; Tho, Tam ; Valenti, Terri</creatorcontrib><description>The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a high-speed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created. The Research Reference Platform (RRP) is a Myrinet^(TM) cluster of PCs with PCI-based FPGA accelerators (SLAAC-1). The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPC^(TM) nodes with VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad- PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for successful ACS technology insertions is source-code compatibility between the RRP and DRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2 accelerators and how the network-centric SLAAC system-level architecture has shaped their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.</description><identifier>ISSN: 1065-514X</identifier><identifier>DOI: 10.1155/2000/28323</identifier><language>eng</language><publisher>Hindawi Limiteds</publisher><ispartof>VLSI Design, 2000-01, Vol.2000 (3), p.c265-279</ispartof><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-a331t-a41cf4cb512fc2cfcf5298685ff1cda2d8b4b29afce08a810269b992ee1249f53</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27922,27923</link.rule.ids></links><search><creatorcontrib>Schott, Brian</creatorcontrib><creatorcontrib>Crago, Stephen P</creatorcontrib><creatorcontrib>Parker, Robert H</creatorcontrib><creatorcontrib>Chen, Chen H</creatorcontrib><creatorcontrib>Carter, Lauretta C</creatorcontrib><creatorcontrib>Czarnaski, Joseph P</creatorcontrib><creatorcontrib>French, Matthew</creatorcontrib><creatorcontrib>Hom, Ivan</creatorcontrib><creatorcontrib>Tho, Tam</creatorcontrib><creatorcontrib>Valenti, Terri</creatorcontrib><title>Reconfigurable Architectures for System Level Applications of Adaptive Computing</title><title>VLSI Design</title><description>The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a high-speed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created. The Research Reference Platform (RRP) is a Myrinet^(TM) cluster of PCs with PCI-based FPGA accelerators (SLAAC-1). The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPC^(TM) nodes with VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad- PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for successful ACS technology insertions is source-code compatibility between the RRP and DRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2 accelerators and how the network-centric SLAAC system-level architecture has shaped their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.</description><issn>1065-514X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2000</creationdate><recordtype>article</recordtype><recordid>eNpVkE1LxDAYhHNQcF29-Aty8lbN-7aJzbEsfsGKix_graTZN2uWblObdMF_b2W9eBoGHmaGYewCxBWAlNcohLjGMsf8iM1AKJlJKD5O2GmMWyGgmKAZW72QDZ3zm3EwTUu8GuynT2TTOFDkLgz89Tsm2vEl7anlVd-33prkQxd5cLxamz75PfFF2PVj8t3mjB0700Y6_9M5e7-7fVs8ZMvn-8dFtcxMnkPKTAHWFbaRgM6iddZJ1KUqpXNg1wbXZVM0qI2zJEpTgkClG62RCLDQTuZzdnnI7YfwNVJM9c5HS21rOgpjrPFGKS2VmMCnA2j84JOvt2EcumlZvUIBUz1OP6n69yzASUABQi4Ewn9jUckpVOc_i0dlVg</recordid><startdate>20000101</startdate><enddate>20000101</enddate><creator>Schott, Brian</creator><creator>Crago, Stephen P</creator><creator>Parker, Robert H</creator><creator>Chen, Chen H</creator><creator>Carter, Lauretta C</creator><creator>Czarnaski, Joseph P</creator><creator>French, Matthew</creator><creator>Hom, Ivan</creator><creator>Tho, Tam</creator><creator>Valenti, Terri</creator><general>Hindawi Limiteds</general><scope>188</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20000101</creationdate><title>Reconfigurable Architectures for System Level Applications of Adaptive Computing</title><author>Schott, Brian ; Crago, Stephen P ; Parker, Robert H ; Chen, Chen H ; Carter, Lauretta C ; Czarnaski, Joseph P ; French, Matthew ; Hom, Ivan ; Tho, Tam ; Valenti, Terri</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a331t-a41cf4cb512fc2cfcf5298685ff1cda2d8b4b29afce08a810269b992ee1249f53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2000</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Schott, Brian</creatorcontrib><creatorcontrib>Crago, Stephen P</creatorcontrib><creatorcontrib>Parker, Robert H</creatorcontrib><creatorcontrib>Chen, Chen H</creatorcontrib><creatorcontrib>Carter, Lauretta C</creatorcontrib><creatorcontrib>Czarnaski, Joseph P</creatorcontrib><creatorcontrib>French, Matthew</creatorcontrib><creatorcontrib>Hom, Ivan</creatorcontrib><creatorcontrib>Tho, Tam</creatorcontrib><creatorcontrib>Valenti, Terri</creatorcontrib><collection>Airiti Library</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>VLSI Design</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Schott, Brian</au><au>Crago, Stephen P</au><au>Parker, Robert H</au><au>Chen, Chen H</au><au>Carter, Lauretta C</au><au>Czarnaski, Joseph P</au><au>French, Matthew</au><au>Hom, Ivan</au><au>Tho, Tam</au><au>Valenti, Terri</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Reconfigurable Architectures for System Level Applications of Adaptive Computing</atitle><jtitle>VLSI Design</jtitle><date>2000-01-01</date><risdate>2000</risdate><volume>2000</volume><issue>3</issue><spage>c265</spage><epage>279</epage><pages>c265-279</pages><issn>1065-514X</issn><abstract>The System Level Applications of Adaptive Computing (SLAAC) project is defining an open, distributed, scalable, adaptive computing systems architecture based on a high-speed network cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementations of this architecture are being created. The Research Reference Platform (RRP) is a Myrinet^(TM) cluster of PCs with PCI-based FPGA accelerators (SLAAC-1). The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPC^(TM) nodes with VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad- PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for successful ACS technology insertions is source-code compatibility between the RRP and DRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2 accelerators and how the network-centric SLAAC system-level architecture has shaped their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target Recognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.</abstract><pub>Hindawi Limiteds</pub><doi>10.1155/2000/28323</doi><tpages>15</tpages><oa>free_for_read</oa></addata></record> |
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| title | Reconfigurable Architectures for System Level Applications of Adaptive Computing |
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