An extraction-based verification methodology for MEMS
Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an ext...
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Veröffentlicht in: | Journal of microelectromechanical systems 2002-02, Vol.11 (1), p.2-11 |
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description | Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity. |
doi_str_mv | 10.1109/84.982857 |
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These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity.</description><identifier>ISSN: 1057-7157</identifier><identifier>EISSN: 1941-0158</identifier><identifier>DOI: 10.1109/84.982857</identifier><identifier>CODEN: JMIYET</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Actuators ; Algorithms ; Applied sciences ; Boundary element method ; Circuit design ; Circuit simulation ; Circuits ; Computer aided design ; Computer science; control theory; systems ; Computer simulation ; Design ; Design engineering ; Equivalent circuits ; Exact sciences and technology ; Extraction ; Finite element method ; Geometry ; Government ; Instruments, apparatus, components and techniques common to several branches of physics and astronomy ; Integrated circuit interconnections ; Integrated circuit layout ; Mechanical engineering. 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These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity.</description><subject>Actuators</subject><subject>Algorithms</subject><subject>Applied sciences</subject><subject>Boundary element method</subject><subject>Circuit design</subject><subject>Circuit simulation</subject><subject>Circuits</subject><subject>Computer aided design</subject><subject>Computer science; control theory; systems</subject><subject>Computer simulation</subject><subject>Design</subject><subject>Design engineering</subject><subject>Equivalent circuits</subject><subject>Exact sciences and technology</subject><subject>Extraction</subject><subject>Finite element method</subject><subject>Geometry</subject><subject>Government</subject><subject>Instruments, apparatus, components and techniques common to several branches of physics and astronomy</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuit layout</subject><subject>Mechanical engineering. Machine design</subject><subject>Mechanical instruments, equipment and techniques</subject><subject>Methodology</subject><subject>Microactuators</subject><subject>Microelectromechanical systems</subject><subject>Micromechanical devices</subject><subject>Micromechanical devices and systems</subject><subject>Microsensors</subject><subject>Parasitic capacitance</subject><subject>Physics</subject><subject>Precision engineering, watch making</subject><subject>Productivity</subject><subject>Representations</subject><subject>Schematic diagrams</subject><subject>Sensor systems</subject><subject>Software</subject><subject>Studies</subject><subject>Very large scale integration</subject><subject>VLSI circuits</subject><issn>1057-7157</issn><issn>1941-0158</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0UtLAzEUBeBBFKzVhVtXg-BrMTV38l6WUh_Q4kJdD2l6R6dMJzWZiv33prQouKirhOTLIdyTJKdAegBE3yrW0ypXXO4lHdAMMgJc7cc94TKTwOVhchTCjBBgTIlOwvtNil-tN7atXJNNTMBp-om-Kitr1kfpHNt3N3W1e1ulpfPpeDh-Pk4OSlMHPNmu3eT1bvgyeMhGT_ePg_4os4ySNpPWGElzjjilbKIoV5KSPM8ZJ4wrZpFpPWUCjSSWKUkiKCkogbTMhaBAu8nVJnfh3ccSQ1vMq2Cxrk2DbhkKyQTRwAmJ8nKnjCMBznP4H0qRMwLrxOudEIQESjlVNNLzP3Tmlr6Jkym00LEWKkVENxtkvQvBY1ksfDU3flUAKdbdFYoVm-6ivdgGmmBNXXrT2Cr8PqBMCC3XfzzbuAoRf663Id-gZ5wQ</recordid><startdate>20020201</startdate><enddate>20020201</enddate><creator>Baidya, B.</creator><creator>Gupta, S.K.</creator><creator>Mukherjee, T.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Machine design</topic><topic>Mechanical instruments, equipment and techniques</topic><topic>Methodology</topic><topic>Microactuators</topic><topic>Microelectromechanical systems</topic><topic>Micromechanical devices</topic><topic>Micromechanical devices and systems</topic><topic>Microsensors</topic><topic>Parasitic capacitance</topic><topic>Physics</topic><topic>Precision engineering, watch making</topic><topic>Productivity</topic><topic>Representations</topic><topic>Schematic diagrams</topic><topic>Sensor systems</topic><topic>Software</topic><topic>Studies</topic><topic>Very large scale integration</topic><topic>VLSI circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Baidya, B.</creatorcontrib><creatorcontrib>Gupta, S.K.</creatorcontrib><creatorcontrib>Mukherjee, T.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Aerospace Database</collection><collection>Mechanical Engineering Abstracts</collection><jtitle>Journal of microelectromechanical systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Baidya, B.</au><au>Gupta, S.K.</au><au>Mukherjee, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An extraction-based verification methodology for MEMS</atitle><jtitle>Journal of microelectromechanical systems</jtitle><stitle>JMEMS</stitle><date>2002-02-01</date><risdate>2002</risdate><volume>11</volume><issue>1</issue><spage>2</spage><epage>11</epage><pages>2-11</pages><issn>1057-7157</issn><eissn>1941-0158</eissn><coden>JMIYET</coden><abstract>Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/84.982857</doi><tpages>10</tpages></addata></record> |
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subjects | Actuators Algorithms Applied sciences Boundary element method Circuit design Circuit simulation Circuits Computer aided design Computer science control theory systems Computer simulation Design Design engineering Equivalent circuits Exact sciences and technology Extraction Finite element method Geometry Government Instruments, apparatus, components and techniques common to several branches of physics and astronomy Integrated circuit interconnections Integrated circuit layout Mechanical engineering. Machine design Mechanical instruments, equipment and techniques Methodology Microactuators Microelectromechanical systems Micromechanical devices Micromechanical devices and systems Microsensors Parasitic capacitance Physics Precision engineering, watch making Productivity Representations Schematic diagrams Sensor systems Software Studies Very large scale integration VLSI circuits |
title | An extraction-based verification methodology for MEMS |
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