Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors

A generic multiplication scheme for the low power VLSI implementation of the DCT is described in this paper. The scheme concurrently processes blocks of cosine coefficient and pixel values during the multiplication procedure, with the aim of reducing the total switched capacitance within the multipl...

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Veröffentlicht in:	VLSI Design 2000-01, Vol.2000 (4), p.397-403
Hauptverfasser:	Masupe, S., Arslan, T.
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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