CVD Al/PVD Al integration for advanced via and interconnect technology
A metallization process that can fill the ever-shrinking vias and form the interconnect at the same time is highly desirable. An integrated Al plug and interconnect process offers advantages of improved electrical performance, and reduced cost of ownership through process simplification for 0.25 μm...
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| Veröffentlicht in: | Thin solid films 1998-05, Vol.320 (1), p.35-44 |
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| creator | Beinglass, Israel Naik, Mehul |
| description | A metallization process that can fill the ever-shrinking vias and form the interconnect at the same time is highly desirable. An integrated Al plug and interconnect process offers advantages of improved electrical performance, and reduced cost of ownership through process simplification for 0.25
μm and beyond. In this report, an enabling technology that integrates Al deposited by chemical vapor deposition (CVD) with an overlayer of sputtered AlCu is discussed. The ability to deposit in-situ sequential layers without a vacuum break was a key factor in developing a technology for consistent void-free fill of sub-0.25
μm structures. This approach has resulted in a low resistivity (∼3
μΩ cm), low temperature ( |
| doi_str_mv | 10.1016/S0040-6090(97)01063-8 |
| format | Article |
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μm and beyond. In this report, an enabling technology that integrates Al deposited by chemical vapor deposition (CVD) with an overlayer of sputtered AlCu is discussed. The ability to deposit in-situ sequential layers without a vacuum break was a key factor in developing a technology for consistent void-free fill of sub-0.25
μm structures. This approach has resulted in a low resistivity (∼3
μΩ cm), low temperature (<380°C) via fill process with copper doping of CVD Al. Sub-0.2
μm via/contact fill with aspect ratio greater than 4 was achieved. This technology was integrated in a two-level 0.35
μm design rule with conventional BEOL processing. A better than 2× improvement in via resistance was achieved compared to W technology. No problems were encountered with oxide CMP, photolithography or metal etch. Data on via fill capability and electrical performance of the integrated CVD Al/PVD AlCu process is presented. Studies on copper doping of CVD Al are discussed. Investigation of morphology and texture dependence on wetting layer for CVD Al is reported.</description><identifier>ISSN: 0040-6090</identifier><identifier>EISSN: 1879-2731</identifier><identifier>DOI: 10.1016/S0040-6090(97)01063-8</identifier><identifier>CODEN: THSFAP</identifier><language>eng</language><publisher>Lausanne: Elsevier B.V</publisher><subject>Applied sciences ; CVD Al/PVD Al integration ; Electronics ; Exact sciences and technology ; Metallization ; Microelectronic fabrication (materials and surfaces technology) ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Vias</subject><ispartof>Thin solid films, 1998-05, Vol.320 (1), p.35-44</ispartof><rights>1998 Elsevier Science S.A.</rights><rights>1998 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c433t-222684bc3086eadbe18f5e9742a2777f6b997d1bc4b6658b5cdb2b07e5215c363</citedby><cites>FETCH-LOGICAL-c433t-222684bc3086eadbe18f5e9742a2777f6b997d1bc4b6658b5cdb2b07e5215c363</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0040609097010638$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,3537,23909,23910,25118,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=2391537$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Beinglass, Israel</creatorcontrib><creatorcontrib>Naik, Mehul</creatorcontrib><title>CVD Al/PVD Al integration for advanced via and interconnect technology</title><title>Thin solid films</title><description>A metallization process that can fill the ever-shrinking vias and form the interconnect at the same time is highly desirable. An integrated Al plug and interconnect process offers advantages of improved electrical performance, and reduced cost of ownership through process simplification for 0.25
μm and beyond. In this report, an enabling technology that integrates Al deposited by chemical vapor deposition (CVD) with an overlayer of sputtered AlCu is discussed. The ability to deposit in-situ sequential layers without a vacuum break was a key factor in developing a technology for consistent void-free fill of sub-0.25
μm structures. This approach has resulted in a low resistivity (∼3
μΩ cm), low temperature (<380°C) via fill process with copper doping of CVD Al. Sub-0.2
μm via/contact fill with aspect ratio greater than 4 was achieved. This technology was integrated in a two-level 0.35
μm design rule with conventional BEOL processing. A better than 2× improvement in via resistance was achieved compared to W technology. No problems were encountered with oxide CMP, photolithography or metal etch. Data on via fill capability and electrical performance of the integrated CVD Al/PVD AlCu process is presented. Studies on copper doping of CVD Al are discussed. Investigation of morphology and texture dependence on wetting layer for CVD Al is reported.</description><subject>Applied sciences</subject><subject>CVD Al/PVD Al integration</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Metallization</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Vias</subject><issn>0040-6090</issn><issn>1879-2731</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><recordid>eNqFkEtLAzEUhYMoWKs_QZiFiC7G5jGTTFZSqlWhoOBjG5LMnRqZTmoyLfTfO52Wbl2dzXfv4XwIXRJ8RzDho3eMM5xyLPGNFLeYYM7S4ggNSCFkSgUjx2hwQE7RWYw_GGNCKRug6eTrIRnXo7c-Ete0MA-6db5JKh8SXa51Y6FM1k4nuil7IFjfNGDbpAX73fjazzfn6KTSdYSLfQ7R5_TxY_Kczl6fXibjWWozxtqUUsqLzFiGCw66NECKKgcpMqqpEKLiRkpREmMzw3lemNyWhhosIKckt4yzIbre_V0G_7uC2KqFixbqWjfgV1FRkQkhOe7AfAfa4GMMUKllcAsdNopgtbWmemtqq0RJoXprqujurvYFOlpdV6Gb7-LhmDJJciY67H6HQTd27SCoaB1sTbnQmVGld_8U_QH3an9m</recordid><startdate>19980504</startdate><enddate>19980504</enddate><creator>Beinglass, Israel</creator><creator>Naik, Mehul</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19980504</creationdate><title>CVD Al/PVD Al integration for advanced via and interconnect technology</title><author>Beinglass, Israel ; Naik, Mehul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c433t-222684bc3086eadbe18f5e9742a2777f6b997d1bc4b6658b5cdb2b07e5215c363</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Applied sciences</topic><topic>CVD Al/PVD Al integration</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Metallization</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Vias</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Beinglass, Israel</creatorcontrib><creatorcontrib>Naik, Mehul</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Thin solid films</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Beinglass, Israel</au><au>Naik, Mehul</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>CVD Al/PVD Al integration for advanced via and interconnect technology</atitle><jtitle>Thin solid films</jtitle><date>1998-05-04</date><risdate>1998</risdate><volume>320</volume><issue>1</issue><spage>35</spage><epage>44</epage><pages>35-44</pages><issn>0040-6090</issn><eissn>1879-2731</eissn><coden>THSFAP</coden><abstract>A metallization process that can fill the ever-shrinking vias and form the interconnect at the same time is highly desirable. An integrated Al plug and interconnect process offers advantages of improved electrical performance, and reduced cost of ownership through process simplification for 0.25
μm and beyond. In this report, an enabling technology that integrates Al deposited by chemical vapor deposition (CVD) with an overlayer of sputtered AlCu is discussed. The ability to deposit in-situ sequential layers without a vacuum break was a key factor in developing a technology for consistent void-free fill of sub-0.25
μm structures. This approach has resulted in a low resistivity (∼3
μΩ cm), low temperature (<380°C) via fill process with copper doping of CVD Al. Sub-0.2
μm via/contact fill with aspect ratio greater than 4 was achieved. This technology was integrated in a two-level 0.35
μm design rule with conventional BEOL processing. A better than 2× improvement in via resistance was achieved compared to W technology. No problems were encountered with oxide CMP, photolithography or metal etch. Data on via fill capability and electrical performance of the integrated CVD Al/PVD AlCu process is presented. Studies on copper doping of CVD Al are discussed. Investigation of morphology and texture dependence on wetting layer for CVD Al is reported.</abstract><cop>Lausanne</cop><pub>Elsevier B.V</pub><doi>10.1016/S0040-6090(97)01063-8</doi><tpages>10</tpages></addata></record> |
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| ispartof | Thin solid films, 1998-05, Vol.320 (1), p.35-44 |
| issn | 0040-6090 1879-2731 |
| language | eng |
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| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences CVD Al/PVD Al integration Electronics Exact sciences and technology Metallization Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Vias |
| title | CVD Al/PVD Al integration for advanced via and interconnect technology |
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