Energy models for delay testing
We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It al...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1995-06, Vol.14 (6), p.728-739 |
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description | We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It allows the design of a special class of delay fault testable circuits, called (k,K)-circuits, that have polynomial-time test generation complexity. For the new formulation, the relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function. The minimum-energy states of this function correspond to signal values that are consistent with the gate's logic function. The function also implicitly includes the information about the potential hazards due to arbitrary delay distributions in the circuit. The energy function for the circuit is the summation of the individual gate energy functions. To derive tests for a given delay fault, this function is suitably modified such that any minimum-energy state is guaranteed to be a test. The specific modifications to the energy function depend on the type (robust or nonrobust, with or without hazards) of delay test desired. For (k, K)-circuits, we show that the energy function can be minimized in polynomial-time. For general circuits, where the problem still has an exponential complexity, the recently proposed transitive closure based test generation technique is very effective in generating tests. This approach efficiently determines a delay test or establishes that no test is possible for the given delay fault. We report experimental results on various sequential benchmark circuits (full-scan versions) showing the feasibility and practicality of the new methods.< > |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_27467364</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>387733</ieee_id><sourcerecordid>27467364</sourcerecordid><originalsourceid>FETCH-LOGICAL-c308t-633fce39f4d89e089fdd423d1e4d65dce204ddc558d8b0b2207a01a8a54f76e33</originalsourceid><addsrcrecordid>eNpFkE1LAzEQhoMoWKsHr17cgwgetk4yySZ7lFI_oOBFzyFNJmVlu1uT9tB_78oWPc3APO8z8DJ2zWHGOdSPEmdotEY8YRNeoy4lV_yUTUBoUwJoOGcXOX8BcKlEPWG3i47S-lBs-kBtLmKfimFxh2JHedd060t2Fl2b6eo4p-zzefExfy2X7y9v86dl6RHMrqwQoyesowymJjB1DEEKDJxkqFTwJECG4JUywaxgJQRoB9wZp2TUFSFO2f3o3ab-ez_8tpsme2pb11G_z1ZoWWms5AA-jKBPfc6Jot2mZuPSwXKwvxVYiXasYGDvjlKXvWtjcp1v8l8AlahgsE7ZzYg1RPR_HR0_1_ZhUw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27467364</pqid></control><display><type>article</type><title>Energy models for delay testing</title><source>IEEE Electronic Library (IEL)</source><creator>Chakradhar, S.T. ; Iyer, M.A. ; Agrawal, V.D.</creator><creatorcontrib>Chakradhar, S.T. ; Iyer, M.A. ; Agrawal, V.D.</creatorcontrib><description>We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It allows the design of a special class of delay fault testable circuits, called (k,K)-circuits, that have polynomial-time test generation complexity. For the new formulation, the relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function. The minimum-energy states of this function correspond to signal values that are consistent with the gate's logic function. The function also implicitly includes the information about the potential hazards due to arbitrary delay distributions in the circuit. The energy function for the circuit is the summation of the individual gate energy functions. To derive tests for a given delay fault, this function is suitably modified such that any minimum-energy state is guaranteed to be a test. The specific modifications to the energy function depend on the type (robust or nonrobust, with or without hazards) of delay test desired. For (k, K)-circuits, we show that the energy function can be minimized in polynomial-time. For general circuits, where the problem still has an exponential complexity, the recently proposed transitive closure based test generation technique is very effective in generating tests. This approach efficiently determines a delay test or establishes that no test is possible for the given delay fault. We report experimental results on various sequential benchmark circuits (full-scan versions) showing the feasibility and practicality of the new methods.< ></description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.387733</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit faults ; Circuit testing ; Delay ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Hazards ; Integrated circuits ; Logic gates ; Minimization ; Polynomials ; Robustness ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Sequential analysis ; Sequential circuits</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 1995-06, Vol.14 (6), p.728-739</ispartof><rights>1995 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c308t-633fce39f4d89e089fdd423d1e4d65dce204ddc558d8b0b2207a01a8a54f76e33</citedby><cites>FETCH-LOGICAL-c308t-633fce39f4d89e089fdd423d1e4d65dce204ddc558d8b0b2207a01a8a54f76e33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/387733$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/387733$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3526067$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Chakradhar, S.T.</creatorcontrib><creatorcontrib>Iyer, M.A.</creatorcontrib><creatorcontrib>Agrawal, V.D.</creatorcontrib><title>Energy models for delay testing</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It allows the design of a special class of delay fault testable circuits, called (k,K)-circuits, that have polynomial-time test generation complexity. For the new formulation, the relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function. The minimum-energy states of this function correspond to signal values that are consistent with the gate's logic function. The function also implicitly includes the information about the potential hazards due to arbitrary delay distributions in the circuit. The energy function for the circuit is the summation of the individual gate energy functions. To derive tests for a given delay fault, this function is suitably modified such that any minimum-energy state is guaranteed to be a test. The specific modifications to the energy function depend on the type (robust or nonrobust, with or without hazards) of delay test desired. For (k, K)-circuits, we show that the energy function can be minimized in polynomial-time. For general circuits, where the problem still has an exponential complexity, the recently proposed transitive closure based test generation technique is very effective in generating tests. This approach efficiently determines a delay test or establishes that no test is possible for the given delay fault. We report experimental results on various sequential benchmark circuits (full-scan versions) showing the feasibility and practicality of the new methods.< ></description><subject>Applied sciences</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Delay</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hazards</subject><subject>Integrated circuits</subject><subject>Logic gates</subject><subject>Minimization</subject><subject>Polynomials</subject><subject>Robustness</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Sequential analysis</subject><subject>Sequential circuits</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1995</creationdate><recordtype>article</recordtype><recordid>eNpFkE1LAzEQhoMoWKsHr17cgwgetk4yySZ7lFI_oOBFzyFNJmVlu1uT9tB_78oWPc3APO8z8DJ2zWHGOdSPEmdotEY8YRNeoy4lV_yUTUBoUwJoOGcXOX8BcKlEPWG3i47S-lBs-kBtLmKfimFxh2JHedd060t2Fl2b6eo4p-zzefExfy2X7y9v86dl6RHMrqwQoyesowymJjB1DEEKDJxkqFTwJECG4JUywaxgJQRoB9wZp2TUFSFO2f3o3ab-ez_8tpsme2pb11G_z1ZoWWms5AA-jKBPfc6Jot2mZuPSwXKwvxVYiXasYGDvjlKXvWtjcp1v8l8AlahgsE7ZzYg1RPR_HR0_1_ZhUw</recordid><startdate>19950601</startdate><enddate>19950601</enddate><creator>Chakradhar, S.T.</creator><creator>Iyer, M.A.</creator><creator>Agrawal, V.D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19950601</creationdate><title>Energy models for delay testing</title><author>Chakradhar, S.T. ; Iyer, M.A. ; Agrawal, V.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c308t-633fce39f4d89e089fdd423d1e4d65dce204ddc558d8b0b2207a01a8a54f76e33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Applied sciences</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Delay</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hazards</topic><topic>Integrated circuits</topic><topic>Logic gates</topic><topic>Minimization</topic><topic>Polynomials</topic><topic>Robustness</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Sequential analysis</topic><topic>Sequential circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chakradhar, S.T.</creatorcontrib><creatorcontrib>Iyer, M.A.</creatorcontrib><creatorcontrib>Agrawal, V.D.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chakradhar, S.T.</au><au>Iyer, M.A.</au><au>Agrawal, V.D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Energy models for delay testing</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1995-06-01</date><risdate>1995</risdate><volume>14</volume><issue>6</issue><spage>728</spage><epage>739</epage><pages>728-739</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>We present a new formulation of the delay testing problem as an energy minimization problem. Two important applications have motivated this work. First, it can be used to efficiently generate robust and nonrobust tests for path delay faults in scan and hold type of sequential circuits. Second, It allows the design of a special class of delay fault testable circuits, called (k,K)-circuits, that have polynomial-time test generation complexity. For the new formulation, the relationship between input and output signal states of a logic gate for an arbitrary pair of input vectors is expressed through an energy function. The minimum-energy states of this function correspond to signal values that are consistent with the gate's logic function. The function also implicitly includes the information about the potential hazards due to arbitrary delay distributions in the circuit. The energy function for the circuit is the summation of the individual gate energy functions. To derive tests for a given delay fault, this function is suitably modified such that any minimum-energy state is guaranteed to be a test. The specific modifications to the energy function depend on the type (robust or nonrobust, with or without hazards) of delay test desired. For (k, K)-circuits, we show that the energy function can be minimized in polynomial-time. For general circuits, where the problem still has an exponential complexity, the recently proposed transitive closure based test generation technique is very effective in generating tests. This approach efficiently determines a delay test or establishes that no test is possible for the given delay fault. We report experimental results on various sequential benchmark circuits (full-scan versions) showing the feasibility and practicality of the new methods.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.387733</doi><tpages>12</tpages></addata></record> |
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subjects | Applied sciences Circuit faults Circuit testing Delay Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hazards Integrated circuits Logic gates Minimization Polynomials Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sequential analysis Sequential circuits |
title | Energy models for delay testing |
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