Methodology for ensuring high reliability of VLSI systems

As the complexity and density of VLSI systems increase, the logical test of systems based on stuck-at fault model is not sufficient to guarantee the high reliability of the system. Recently, a new test approach based on current monitoring, called I ddq test, becomes very important since it can overc...

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Veröffentlicht in:	Journal of systems architecture 1997-03, Vol.43 (1), p.111-117
Hauptverfasser:	Kim, Byung-gi, Chang, Hoon, Wan Cho, Jung
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Asynchronous transfer mode Bridge faults Current monitoring Reliability Studies Systems design Testing VLSI
Online-Zugang:	Volltext
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