Symbolic model checking using SAT procedures instead of BDDs

Symbolic model checking using SAT procedures instead of BDDs

In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formula...

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Hauptverfasser: Biere, A., Cimatti, A., Clarke, E. M., Fujita, M., Zhu, Y.
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Hardware > Integrated circuits > Logic circuits
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Cimatti, A.
Clarke, E. M.
Fujita, M.
Zhu, Y.
description In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formulas. In many instances, our SAT-based approach can significantly outperform BDD-based approaches. We observe that SAT-based techniques are particularly efficient in detecting errors in both combinational and sequential designs.
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fullrecord <record><control><sourceid>proquest_acm_b</sourceid><recordid>TN_cdi_proquest_miscellaneous_27161680</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>27161680</sourcerecordid><originalsourceid>FETCH-LOGICAL-a2502-c527770347b26f3618ffb2f620ebd8c629bbfbad412a4f718bd9eadb886be2893</originalsourceid><addsrcrecordid>eNqNkD1PwzAQhi0BElXJyO6JiRSfnfhDYilt-ZAqMbRIbJbt2BCa1BA3A_-eVEFi5YZ7l0fvnR6ELoHMAIryhhElCzEbQhX0BGVKSCglAAOi2CmaEMFkDoS8nqMspQ8yjBCqFHSCbjffrY1N7XAbK99g9-7drt6_4T4d92a-xZ9ddL7qO59wvU8HbyocA75bLtMFOgumST77zSl6uV9tF4_5-vnhaTFf54aWhOaupEIIwgphKQ-MgwzB0sAp8baSjlNlbbCmKoCaIgiQtlLDFSslt55KxaboauwdXvnqfTrotk7ON43Z-9gnTQVw4JL8gca12sa4SxqIPjrSoyM9OhrA63-B2na1D-wHF4hjzA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>27161680</pqid></control><display><type>conference_proceeding</type><title>Symbolic model checking using SAT procedures instead of BDDs</title><source>IEEE Electronic Library (IEL)</source><creator>Biere, A. ; Cimatti, A. ; Clarke, E. M. ; Fujita, M. ; Zhu, Y.</creator><contributor>Irwin, Mary Jane</contributor><creatorcontrib>Biere, A. ; Cimatti, A. ; Clarke, E. M. ; Fujita, M. ; Zhu, Y. ; Irwin, Mary Jane</creatorcontrib><description>In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formulas. In many instances, our SAT-based approach can significantly outperform BDD-based approaches. We observe that SAT-based techniques are particularly efficient in detecting errors in both combinational and sequential designs.</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 9781581131093</identifier><identifier>ISBN: 1581131097</identifier><identifier>DOI: 10.1145/309847.309942</identifier><language>eng</language><publisher>New York, NY, USA: ACM</publisher><subject>Hardware -- Integrated circuits -- Logic circuits</subject><ispartof>Proceedings - ACM IEEE Design Automation Conference, 1999, p.317-320</ispartof><rights>1999 ACM</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-a2502-c527770347b26f3618ffb2f620ebd8c629bbfbad412a4f718bd9eadb886be2893</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>309,310,314,776,780,4010,4036,4037,27900,27901,27902</link.rule.ids></links><search><contributor>Irwin, Mary Jane</contributor><creatorcontrib>Biere, A.</creatorcontrib><creatorcontrib>Cimatti, A.</creatorcontrib><creatorcontrib>Clarke, E. M.</creatorcontrib><creatorcontrib>Fujita, M.</creatorcontrib><creatorcontrib>Zhu, Y.</creatorcontrib><title>Symbolic model checking using SAT procedures instead of BDDs</title><title>Proceedings - ACM IEEE Design Automation Conference</title><description>In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formulas. In many instances, our SAT-based approach can significantly outperform BDD-based approaches. We observe that SAT-based techniques are particularly efficient in detecting errors in both combinational and sequential designs.</description><subject>Hardware -- Integrated circuits -- Logic circuits</subject><issn>0738-100X</issn><isbn>9781581131093</isbn><isbn>1581131097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNqNkD1PwzAQhi0BElXJyO6JiRSfnfhDYilt-ZAqMbRIbJbt2BCa1BA3A_-eVEFi5YZ7l0fvnR6ELoHMAIryhhElCzEbQhX0BGVKSCglAAOi2CmaEMFkDoS8nqMspQ8yjBCqFHSCbjffrY1N7XAbK99g9-7drt6_4T4d92a-xZ9ddL7qO59wvU8HbyocA75bLtMFOgumST77zSl6uV9tF4_5-vnhaTFf54aWhOaupEIIwgphKQ-MgwzB0sAp8baSjlNlbbCmKoCaIgiQtlLDFSslt55KxaboauwdXvnqfTrotk7ON43Z-9gnTQVw4JL8gca12sa4SxqIPjrSoyM9OhrA63-B2na1D-wHF4hjzA</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Biere, A.</creator><creator>Cimatti, A.</creator><creator>Clarke, E. M.</creator><creator>Fujita, M.</creator><creator>Zhu, Y.</creator><general>ACM</general><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>1999</creationdate><title>Symbolic model checking using SAT procedures instead of BDDs</title><author>Biere, A. ; Cimatti, A. ; Clarke, E. M. ; Fujita, M. ; Zhu, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a2502-c527770347b26f3618ffb2f620ebd8c629bbfbad412a4f718bd9eadb886be2893</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Hardware -- Integrated circuits -- Logic circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Biere, A.</creatorcontrib><creatorcontrib>Cimatti, A.</creatorcontrib><creatorcontrib>Clarke, E. M.</creatorcontrib><creatorcontrib>Fujita, M.</creatorcontrib><creatorcontrib>Zhu, Y.</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Biere, A.</au><au>Cimatti, A.</au><au>Clarke, E. M.</au><au>Fujita, M.</au><au>Zhu, Y.</au><au>Irwin, Mary Jane</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Symbolic model checking using SAT procedures instead of BDDs</atitle><btitle>Proceedings - ACM IEEE Design Automation Conference</btitle><date>1999</date><risdate>1999</risdate><spage>317</spage><epage>320</epage><pages>317-320</pages><issn>0738-100X</issn><isbn>9781581131093</isbn><isbn>1581131097</isbn><abstract>In this paper, we study the application of propositional decision procedures in hardware verification. In particular, we apply bounded model checking, as introduced in [1], to equivalence and invariant checking. We present several optimizations that reduce the size of generated propositional formulas. In many instances, our SAT-based approach can significantly outperform BDD-based approaches. We observe that SAT-based techniques are particularly efficient in detecting errors in both combinational and sequential designs.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/309847.309942</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record>
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subjects Hardware -- Integrated circuits -- Logic circuits
title Symbolic model checking using SAT procedures instead of BDDs
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T13%3A00%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_acm_b&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Symbolic%20model%20checking%20using%20SAT%20procedures%20instead%20of%20BDDs&rft.btitle=Proceedings%20-%20ACM%20IEEE%20Design%20Automation%20Conference&rft.au=Biere,%20A.&rft.date=1999&rft.spage=317&rft.epage=320&rft.pages=317-320&rft.issn=0738-100X&rft.isbn=9781581131093&rft.isbn_list=1581131097&rft_id=info:doi/10.1145/309847.309942&rft_dat=%3Cproquest_acm_b%3E27161680%3C/proquest_acm_b%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27161680&rft_id=info:pmid/&rfr_iscdi=true