High yielding self-aligned contact process for a 0.150-μm DRAM technology

This paper describes improvements in the self-aligned contact process for 0.150 mu m and 0.175 mu m technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 mu m ground rules and beyond by using a C sub(4)F sub(8)-CH sub(2)F...

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Veröffentlicht in:	IEEE transactions on semiconductor manufacturing 2002-05, Vol.15 (2), p.223-228
Hauptverfasser:	RUPP, Thomas S, DOBUZINSKY, David, ZHIJIAN LU, SARDESAI, Viraj Y, LIU, Hang-Yip, MALDEI, Michael, FALTERMEIER, John, GAMBINO, Jeff
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Aspect ratio Contact Dynamic random access memory Electronics Etching Exact sciences and technology Gates Grounds Integrated circuits Integrated circuits by function (including memories and processors) Lithography Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors
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