Algorithm for determining repetitive patterns in very large IC layouts

Algorithm for determining repetitive patterns in very large IC layouts

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling...

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Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1999-01, Vol.46 (3), p.494-501
Hauptverfasser: Niewczas, Mariusz, Maly, Wojciech, Strojwas, Andrzej
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container_title IEEE transactions on circuits and systems. 2, Analog and digital signal processing
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creator Niewczas, Mariusz
Maly, Wojciech
Strojwas, Andrzej
description This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size.
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title Algorithm for determining repetitive patterns in very large IC layouts
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