Converting a 64 b PowerPC processor from CMOS bulk to SOI technology

A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI...

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Hauptverfasser: Allen, D, Behrends, D, Stanisic, B
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Behrends, D
Stanisic, B
description A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.
doi_str_mv 10.1145/309847.310094
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fullrecord <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_26899696</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>26899696</sourcerecordid><originalsourceid>FETCH-LOGICAL-p99t-a6842cb8c5bede45257f83c745ca67a7971824fb464de1d2bc30022302b2cbaf3</originalsourceid><addsrcrecordid>eNotjjtPwzAURj2A1FI6st-JLcWPGz9GFB6tVJRK7cBW2Y5TCmlc4gTEvycSTJ_OcI4-Qm4YXTCG-Z2gRqNaCEapwQsypUrobITXCblK6Z1SikyyKXkoYvsVuv7YHsCCRHCwid-h2xRw7qIPKcUO6i6eoHgpt-CG5gP6CNtyBX3wb21s4uHnmlzWtklh_r8zsnt63BXLbF0-r4r7dXY2ps-s1Mi90z53oQqY81zVWniFubdSWWUU0xxrhxKrwCruvKCUc0G5GzVbixm5_cuOzz6HkPr96Zh8aBrbhjikPZfaGGmk-AUsT0of</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>26899696</pqid></control><display><type>conference_proceeding</type><title>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</title><source>IEEE Electronic Library (IEL)</source><creator>Allen, D ; Behrends, D ; Stanisic, B</creator><creatorcontrib>Allen, D ; Behrends, D ; Stanisic, B</creatorcontrib><description>A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</description><identifier>ISSN: 0738-100X</identifier><identifier>DOI: 10.1145/309847.310094</identifier><language>eng</language><ispartof>Proceedings - ACM IEEE Design Automation Conference, 1999</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Allen, D</creatorcontrib><creatorcontrib>Behrends, D</creatorcontrib><creatorcontrib>Stanisic, B</creatorcontrib><title>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</title><title>Proceedings - ACM IEEE Design Automation Conference</title><description>A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</description><issn>0738-100X</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNotjjtPwzAURj2A1FI6st-JLcWPGz9GFB6tVJRK7cBW2Y5TCmlc4gTEvycSTJ_OcI4-Qm4YXTCG-Z2gRqNaCEapwQsypUrobITXCblK6Z1SikyyKXkoYvsVuv7YHsCCRHCwid-h2xRw7qIPKcUO6i6eoHgpt-CG5gP6CNtyBX3wb21s4uHnmlzWtklh_r8zsnt63BXLbF0-r4r7dXY2ps-s1Mi90z53oQqY81zVWniFubdSWWUU0xxrhxKrwCruvKCUc0G5GzVbixm5_cuOzz6HkPr96Zh8aBrbhjikPZfaGGmk-AUsT0of</recordid><startdate>19990101</startdate><enddate>19990101</enddate><creator>Allen, D</creator><creator>Behrends, D</creator><creator>Stanisic, B</creator><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19990101</creationdate><title>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</title><author>Allen, D ; Behrends, D ; Stanisic, B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p99t-a6842cb8c5bede45257f83c745ca67a7971824fb464de1d2bc30022302b2cbaf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Allen, D</creatorcontrib><creatorcontrib>Behrends, D</creatorcontrib><creatorcontrib>Stanisic, B</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Allen, D</au><au>Behrends, D</au><au>Stanisic, B</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</atitle><btitle>Proceedings - ACM IEEE Design Automation Conference</btitle><date>1999-01-01</date><risdate>1999</risdate><issn>0738-100X</issn><abstract>A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</abstract><doi>10.1145/309847.310094</doi></addata></record>
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title Converting a 64 b PowerPC processor from CMOS bulk to SOI technology
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T02%3A03%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Converting%20a%2064%20b%20PowerPC%20processor%20from%20CMOS%20bulk%20to%20SOI%20technology&rft.btitle=Proceedings%20-%20ACM%20IEEE%20Design%20Automation%20Conference&rft.au=Allen,%20D&rft.date=1999-01-01&rft.issn=0738-100X&rft_id=info:doi/10.1145/309847.310094&rft_dat=%3Cproquest%3E26899696%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26899696&rft_id=info:pmid/&rfr_iscdi=true