VLSI design in the 3rd dimension

Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Integration (Amsterdam) 1998-09, Vol.25 (1), p.1-16
Hauptverfasser: Strickland, Stephen, Ergin, Erhan, Kaeli, David R., Zavracky, Paul
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 16
container_issue 1
container_start_page 1
container_title Integration (Amsterdam)
container_volume 25
creator Strickland, Stephen
Ergin, Erhan
Kaeli, David R.
Zavracky, Paul
description Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route lengths and die sizes. In this paper we report on our new three-dimensional design technology, devices which we have fabricated, and our move to an automated 3-D design path using Cadence and Synopsys design tools. We present both discussion of functional 3-D devices, and on-going work on VLSI design tools and the implementation of a 3-D microprocessor.
doi_str_mv 10.1016/S0167-9260(98)00006-6
format Article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_26833918</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0167926098000066</els_id><sourcerecordid>26833918</sourcerecordid><originalsourceid>FETCH-LOGICAL-c367t-d2859fd1d1648a134619eaa9cacd78fbc1924a302b63b06889c0e54a79302b613</originalsourceid><addsrcrecordid>eNqFkE1LAzEQhoMoWKs_QdiDiB5W87H5OokUPwoFD1WvIU1mNbLN1mQr-O_ddosencMMDM_My_sidErwFcFEXM_7JktNBb7Q6hL3JUqxh0ZESVpKTuk-Gv0ih-go54-eIZXkI1S8zubTwkMOb7EIsejeoWDJFz4sIebQxmN0UNsmw8lujtHL_d3z5LGcPT1MJ7ez0jEhu9JTxXXtiSeiUpawShAN1mpnnZeqXjiiaWUZpgvBFlgopR0GXlmptzvCxuh8-LtK7ecacmeWITtoGhuhXWdDhWJME9WDfABdanNOUJtVCkubvg3BZpOH2eZhNmaNVmabhxH93dlOwGZnmzrZ6EL-O-ZKcLnBbgYMerNfAZLJLkB04EMC1xnfhn-EfgB_1nEk</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26833918</pqid></control><display><type>article</type><title>VLSI design in the 3rd dimension</title><source>Elsevier ScienceDirect Journals Complete</source><creator>Strickland, Stephen ; Ergin, Erhan ; Kaeli, David R. ; Zavracky, Paul</creator><creatorcontrib>Strickland, Stephen ; Ergin, Erhan ; Kaeli, David R. ; Zavracky, Paul</creatorcontrib><description>Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route lengths and die sizes. In this paper we report on our new three-dimensional design technology, devices which we have fabricated, and our move to an automated 3-D design path using Cadence and Synopsys design tools. We present both discussion of functional 3-D devices, and on-going work on VLSI design tools and the implementation of a 3-D microprocessor.</description><identifier>ISSN: 0167-9260</identifier><identifier>EISSN: 1872-7522</identifier><identifier>DOI: 10.1016/S0167-9260(98)00006-6</identifier><identifier>CODEN: IVJODL</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>3-D microelectronics ; Applied sciences ; Commercial tools ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Integrated circuits ; Layout and routing ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; VLSI CAD</subject><ispartof>Integration (Amsterdam), 1998-09, Vol.25 (1), p.1-16</ispartof><rights>1998 Elsevier Science B.V.</rights><rights>1999 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c367t-d2859fd1d1648a134619eaa9cacd78fbc1924a302b63b06889c0e54a79302b613</citedby><cites>FETCH-LOGICAL-c367t-d2859fd1d1648a134619eaa9cacd78fbc1924a302b63b06889c0e54a79302b613</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/S0167-9260(98)00006-6$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,780,784,3550,27924,27925,45995</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=1586576$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Strickland, Stephen</creatorcontrib><creatorcontrib>Ergin, Erhan</creatorcontrib><creatorcontrib>Kaeli, David R.</creatorcontrib><creatorcontrib>Zavracky, Paul</creatorcontrib><title>VLSI design in the 3rd dimension</title><title>Integration (Amsterdam)</title><description>Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route lengths and die sizes. In this paper we report on our new three-dimensional design technology, devices which we have fabricated, and our move to an automated 3-D design path using Cadence and Synopsys design tools. We present both discussion of functional 3-D devices, and on-going work on VLSI design tools and the implementation of a 3-D microprocessor.</description><subject>3-D microelectronics</subject><subject>Applied sciences</subject><subject>Commercial tools</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Layout and routing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>VLSI CAD</subject><issn>0167-9260</issn><issn>1872-7522</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><recordid>eNqFkE1LAzEQhoMoWKs_QdiDiB5W87H5OokUPwoFD1WvIU1mNbLN1mQr-O_ddosencMMDM_My_sidErwFcFEXM_7JktNBb7Q6hL3JUqxh0ZESVpKTuk-Gv0ih-go54-eIZXkI1S8zubTwkMOb7EIsejeoWDJFz4sIebQxmN0UNsmw8lujtHL_d3z5LGcPT1MJ7ez0jEhu9JTxXXtiSeiUpawShAN1mpnnZeqXjiiaWUZpgvBFlgopR0GXlmptzvCxuh8-LtK7ecacmeWITtoGhuhXWdDhWJME9WDfABdanNOUJtVCkubvg3BZpOH2eZhNmaNVmabhxH93dlOwGZnmzrZ6EL-O-ZKcLnBbgYMerNfAZLJLkB04EMC1xnfhn-EfgB_1nEk</recordid><startdate>19980901</startdate><enddate>19980901</enddate><creator>Strickland, Stephen</creator><creator>Ergin, Erhan</creator><creator>Kaeli, David R.</creator><creator>Zavracky, Paul</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19980901</creationdate><title>VLSI design in the 3rd dimension</title><author>Strickland, Stephen ; Ergin, Erhan ; Kaeli, David R. ; Zavracky, Paul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c367t-d2859fd1d1648a134619eaa9cacd78fbc1924a302b63b06889c0e54a79302b613</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>3-D microelectronics</topic><topic>Applied sciences</topic><topic>Commercial tools</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Layout and routing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>VLSI CAD</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Strickland, Stephen</creatorcontrib><creatorcontrib>Ergin, Erhan</creatorcontrib><creatorcontrib>Kaeli, David R.</creatorcontrib><creatorcontrib>Zavracky, Paul</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Strickland, Stephen</au><au>Ergin, Erhan</au><au>Kaeli, David R.</au><au>Zavracky, Paul</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>VLSI design in the 3rd dimension</atitle><jtitle>Integration (Amsterdam)</jtitle><date>1998-09-01</date><risdate>1998</risdate><volume>25</volume><issue>1</issue><spage>1</spage><epage>16</epage><pages>1-16</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><coden>IVJODL</coden><abstract>Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route lengths and die sizes. In this paper we report on our new three-dimensional design technology, devices which we have fabricated, and our move to an automated 3-D design path using Cadence and Synopsys design tools. We present both discussion of functional 3-D devices, and on-going work on VLSI design tools and the implementation of a 3-D microprocessor.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/S0167-9260(98)00006-6</doi><tpages>16</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0167-9260
ispartof Integration (Amsterdam), 1998-09, Vol.25 (1), p.1-16
issn 0167-9260
1872-7522
language eng
recordid cdi_proquest_miscellaneous_26833918
source Elsevier ScienceDirect Journals Complete
subjects 3-D microelectronics
Applied sciences
Commercial tools
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Layout and routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
VLSI CAD
title VLSI design in the 3rd dimension
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T10%3A23%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=VLSI%20design%20in%20the%203rd%20dimension&rft.jtitle=Integration%20(Amsterdam)&rft.au=Strickland,%20Stephen&rft.date=1998-09-01&rft.volume=25&rft.issue=1&rft.spage=1&rft.epage=16&rft.pages=1-16&rft.issn=0167-9260&rft.eissn=1872-7522&rft.coden=IVJODL&rft_id=info:doi/10.1016/S0167-9260(98)00006-6&rft_dat=%3Cproquest_cross%3E26833918%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26833918&rft_id=info:pmid/&rft_els_id=S0167926098000066&rfr_iscdi=true