A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter
This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1998-12, Vol.33 (12), p.1898-1903 |
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| container_end_page | 1903 |
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| container_issue | 12 |
| container_start_page | 1898 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 33 |
| creator | Opris, I.E. Lewicki, L.D. Wong, B.C. |
| description | This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2/spl times/3.1 mm/sup 2/ in a 0.7 /spl mu/m CMOS process. Several circuit techniques used in this design together with experimental results are presented. |
| doi_str_mv | 10.1109/4.735529 |
| format | Article |
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A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2/spl times/3.1 mm/sup 2/ in a 0.7 /spl mu/m CMOS process. Several circuit techniques used in this design together with experimental results are presented.</description><subject>Capacitors</subject><subject>Circuits</subject><subject>CMOS technology</subject><subject>Error correction</subject><subject>Feedback</subject><subject>Frequency</subject><subject>Linearity</subject><subject>Pipelines</subject><subject>Power dissipation</subject><subject>Throughput</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0M1LxDAQBfAgCq6r4NlTTuIlu5k0SdPjsn6z4kXBW0nTqUSybU26gv-9lS5ePT2G92MOj5Bz4AsAXizlIs-UEsUBmYFShkGevR2SGedgWCE4PyYnKX2Mp5QGZuRxRZNv3wMybGusKQhW-YEKTp-S3fYBl4kmDA1zNvgq2mHEtPc9Bt8iXS2vqevaL4wDxlNy1NiQ8Gyfc_J6e_Oyvmeb57uH9WrDXMb1wGwtalHJDC3XFmSO1kAuK1VolSNXaAxWhc5dDk1mnHO2NhqNFBbrQirg2ZxcTn_72H3uMA3l1ieHIdgWu10qhdGgZSb-h9rwHCSM8GqCLnYpRWzKPvqtjd8l8PJ31VKW06ojvZioR8Q_ti9_ACveb9c</recordid><startdate>19981201</startdate><enddate>19981201</enddate><creator>Opris, I.E.</creator><creator>Lewicki, L.D.</creator><creator>Wong, B.C.</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>7SP</scope></search><sort><creationdate>19981201</creationdate><title>A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter</title><author>Opris, I.E. ; Lewicki, L.D. ; Wong, B.C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-ad2d2b43ea06a147ea8174b59657e05e88eb967c71f38cccad86e842aed945103</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Capacitors</topic><topic>Circuits</topic><topic>CMOS technology</topic><topic>Error correction</topic><topic>Feedback</topic><topic>Frequency</topic><topic>Linearity</topic><topic>Pipelines</topic><topic>Power dissipation</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Opris, I.E.</creatorcontrib><creatorcontrib>Lewicki, L.D.</creatorcontrib><creatorcontrib>Wong, B.C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Opris, I.E.</au><au>Lewicki, L.D.</au><au>Wong, B.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1998-12-01</date><risdate>1998</risdate><volume>33</volume><issue>12</issue><spage>1898</spage><epage>1903</epage><pages>1898-1903</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2/spl times/3.1 mm/sup 2/ in a 0.7 /spl mu/m CMOS process. Several circuit techniques used in this design together with experimental results are presented.</abstract><pub>IEEE</pub><doi>10.1109/4.735529</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 1998-12, Vol.33 (12), p.1898-1903 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26807141 |
| source | IEEE Electronic Library (IEL) |
| subjects | Capacitors Circuits CMOS technology Error correction Feedback Frequency Linearity Pipelines Power dissipation Throughput |
| title | A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter |
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