Long unsigned number systolic serial multipliers and squarers
A systolic serial multiplier and a squarer for unsigned numbers - which operate without zero words inserted between successive data words, output the full product, and have only one clock cycle latency-are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2001-03, Vol.48 (3), p.316-321 |
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| container_title | IEEE transactions on circuits and systems. 2, Analog and digital signal processing |
| container_volume | 48 |
| creator | Pekmestzi, K.Z. Kalivas, P. Moshopoulos, N. |
| description | A systolic serial multiplier and a squarer for unsigned numbers - which operate without zero words inserted between successive data words, output the full product, and have only one clock cycle latency-are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplier cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long number multiplication and squaring. |
| doi_str_mv | 10.1109/82.924075 |
| format | Article |
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| ispartof | IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-03, Vol.48 (3), p.316-321 |
| issn | 1057-7130 1558-125X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Arithmetic Circuits Clocks Computer architecture Cryptography Delay Hardware Merging Pipelines Wiring |
| title | Long unsigned number systolic serial multipliers and squarers |
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