A framework for reconfigurable computing: task scheduling and context management
Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of t...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2001-12, Vol.9 (6), p.858-873 |
---|---|
Hauptverfasser: | , , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 873 |
---|---|
container_issue | 6 |
container_start_page | 858 |
container_title | IEEE transactions on very large scale integration (VLSI) systems |
container_volume | 9 |
creator | Maestre, R. Kurdahi, F.J. Fernandez, M. Hermida, R. Bagherzadeh, N. Singh, H. |
description | Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations. |
doi_str_mv | 10.1109/92.974899 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_26749916</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>974899</ieee_id><sourcerecordid>2631187131</sourcerecordid><originalsourceid>FETCH-LOGICAL-c463t-885061dcec58780f4efe6cf9b5a2d4f7686bfb979f5647b918d27a9102d863aa3</originalsourceid><addsrcrecordid>eNqFkU1LxDAQhoso-Hnw6qkIKh66Jk2aZLwt4hcs6EHPJU0na7VN16RF_fdGdlHwoHOZYeaZdxjeJNmnZEIpgTPIJyC5AlhLtmhRyAxirMeaCJapnJLNZDuEZ0Io50C2kvtpar3u8K33L6ntferR9M4289HrqsXU9N1iHBo3P08HHV7SYJ6wHtvYSLWr49gN-D6knXZ6jh26YTfZsLoNuLfKO8nj1eXDxU02u7u-vZjOMsMFGzKlCiJobdAUSipiOVoUxkJV6LzmVgolKluBBFsILiugqs6lBkryWgmmNdtJTpa6C9-_jhiGsmuCwbbVDvsxlEC5KCgUNJLHf5K5YiTek_-DQnIAKiJ4-At87kfv4rslAKNKSPZ19nQJGd-H4NGWC9902n-UlJRfXpWQl0uvInu0EtTB6DY64kwTfhYYZ7ngLHIHS65BxO_xSuQT8Jea6A</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>993186731</pqid></control><display><type>article</type><title>A framework for reconfigurable computing: task scheduling and context management</title><source>IEEE Electronic Library (IEL)</source><creator>Maestre, R. ; Kurdahi, F.J. ; Fernandez, M. ; Hermida, R. ; Bagherzadeh, N. ; Singh, H.</creator><creatorcontrib>Maestre, R. ; Kurdahi, F.J. ; Fernandez, M. ; Hermida, R. ; Bagherzadeh, N. ; Singh, H.</creatorcontrib><description>Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/92.974899</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Application specific integrated circuits ; Applied sciences ; Architecture ; Automation ; Computer applications ; Concurrent computing ; Design engineering ; Design optimization ; Design. Technologies. Operation analysis. Testing ; Digital signal processing ; Dynamical systems ; Electronics ; Exact sciences and technology ; Hardware ; Integrated circuits ; Management ; Optimization ; Optimization methods ; Process design ; Processor scheduling ; Reconfigurable architectures ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Studies ; Task scheduling</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2001-12, Vol.9 (6), p.858-873</ispartof><rights>2002 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c463t-885061dcec58780f4efe6cf9b5a2d4f7686bfb979f5647b918d27a9102d863aa3</citedby><cites>FETCH-LOGICAL-c463t-885061dcec58780f4efe6cf9b5a2d4f7686bfb979f5647b918d27a9102d863aa3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/974899$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/974899$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=13432643$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Maestre, R.</creatorcontrib><creatorcontrib>Kurdahi, F.J.</creatorcontrib><creatorcontrib>Fernandez, M.</creatorcontrib><creatorcontrib>Hermida, R.</creatorcontrib><creatorcontrib>Bagherzadeh, N.</creatorcontrib><creatorcontrib>Singh, H.</creatorcontrib><title>A framework for reconfigurable computing: task scheduling and context management</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.</description><subject>Application specific integrated circuits</subject><subject>Applied sciences</subject><subject>Architecture</subject><subject>Automation</subject><subject>Computer applications</subject><subject>Concurrent computing</subject><subject>Design engineering</subject><subject>Design optimization</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital signal processing</subject><subject>Dynamical systems</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Management</subject><subject>Optimization</subject><subject>Optimization methods</subject><subject>Process design</subject><subject>Processor scheduling</subject><subject>Reconfigurable architectures</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Studies</subject><subject>Task scheduling</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkU1LxDAQhoso-Hnw6qkIKh66Jk2aZLwt4hcs6EHPJU0na7VN16RF_fdGdlHwoHOZYeaZdxjeJNmnZEIpgTPIJyC5AlhLtmhRyAxirMeaCJapnJLNZDuEZ0Io50C2kvtpar3u8K33L6ntferR9M4289HrqsXU9N1iHBo3P08HHV7SYJ6wHtvYSLWr49gN-D6knXZ6jh26YTfZsLoNuLfKO8nj1eXDxU02u7u-vZjOMsMFGzKlCiJobdAUSipiOVoUxkJV6LzmVgolKluBBFsILiugqs6lBkryWgmmNdtJTpa6C9-_jhiGsmuCwbbVDvsxlEC5KCgUNJLHf5K5YiTek_-DQnIAKiJ4-At87kfv4rslAKNKSPZ19nQJGd-H4NGWC9902n-UlJRfXpWQl0uvInu0EtTB6DY64kwTfhYYZ7ngLHIHS65BxO_xSuQT8Jea6A</recordid><startdate>20011201</startdate><enddate>20011201</enddate><creator>Maestre, R.</creator><creator>Kurdahi, F.J.</creator><creator>Fernandez, M.</creator><creator>Hermida, R.</creator><creator>Bagherzadeh, N.</creator><creator>Singh, H.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20011201</creationdate><title>A framework for reconfigurable computing: task scheduling and context management</title><author>Maestre, R. ; Kurdahi, F.J. ; Fernandez, M. ; Hermida, R. ; Bagherzadeh, N. ; Singh, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c463t-885061dcec58780f4efe6cf9b5a2d4f7686bfb979f5647b918d27a9102d863aa3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Application specific integrated circuits</topic><topic>Applied sciences</topic><topic>Architecture</topic><topic>Automation</topic><topic>Computer applications</topic><topic>Concurrent computing</topic><topic>Design engineering</topic><topic>Design optimization</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital signal processing</topic><topic>Dynamical systems</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Integrated circuits</topic><topic>Management</topic><topic>Optimization</topic><topic>Optimization methods</topic><topic>Process design</topic><topic>Processor scheduling</topic><topic>Reconfigurable architectures</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Studies</topic><topic>Task scheduling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Maestre, R.</creatorcontrib><creatorcontrib>Kurdahi, F.J.</creatorcontrib><creatorcontrib>Fernandez, M.</creatorcontrib><creatorcontrib>Hermida, R.</creatorcontrib><creatorcontrib>Bagherzadeh, N.</creatorcontrib><creatorcontrib>Singh, H.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maestre, R.</au><au>Kurdahi, F.J.</au><au>Fernandez, M.</au><au>Hermida, R.</au><au>Bagherzadeh, N.</au><au>Singh, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A framework for reconfigurable computing: task scheduling and context management</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2001-12-01</date><risdate>2001</risdate><volume>9</volume><issue>6</issue><spage>858</spage><epage>873</epage><pages>858-873</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/92.974899</doi><tpages>16</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1063-8210 |
ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2001-12, Vol.9 (6), p.858-873 |
issn | 1063-8210 1557-9999 |
language | eng |
recordid | cdi_proquest_miscellaneous_26749916 |
source | IEEE Electronic Library (IEL) |
subjects | Application specific integrated circuits Applied sciences Architecture Automation Computer applications Concurrent computing Design engineering Design optimization Design. Technologies. Operation analysis. Testing Digital signal processing Dynamical systems Electronics Exact sciences and technology Hardware Integrated circuits Management Optimization Optimization methods Process design Processor scheduling Reconfigurable architectures Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Studies Task scheduling |
title | A framework for reconfigurable computing: task scheduling and context management |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-09T19%3A35%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20framework%20for%20reconfigurable%20computing:%20task%20scheduling%20and%20context%20management&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Maestre,%20R.&rft.date=2001-12-01&rft.volume=9&rft.issue=6&rft.spage=858&rft.epage=873&rft.pages=858-873&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/92.974899&rft_dat=%3Cproquest_RIE%3E2631187131%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=993186731&rft_id=info:pmid/&rft_ieee_id=974899&rfr_iscdi=true |