I sub(DDQ) testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

This paper presents an I sub(DDQ)-based test strategy for detecting bridging faults in the logic resources of reprogrammable Field Programmable Gate Arrays (FPGAs). The proposed approach utilizes the programmability of the Configurable Logic Blocks (CLBs) to achieve 100 percent coverage of I sub(DDQ)-testable bridging faults. We use a hierarchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables). Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow I sub(DDQ) vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for I sub(DDQ)-testable bridging faults is achieved in five programming phases and 16 I sub(DDQ) vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 I sub(DDQ) measurements.