A vertical MOS-gated Esaki tunneling transistor in silicon

For the first time a vertical, MOS gated tunneling transistor in silicon is fabricated. The necessary sharp doping profile structure is created by means of MBE. Pronounced transistor action due to Esaki tunneling is demonstrated at room temperature. At a low supply voltage of -0.2 V a current gain o...

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Veröffentlicht in:	Thin solid films 2000-07, Vol.369 (1-2), p.387-389
Hauptverfasser:	HANSCH, W, FINK, C, SCHULZE, J, EISELE, I
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Electronics Exact sciences and technology Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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Beschreibung
Zusammenfassung:	For the first time a vertical, MOS gated tunneling transistor in silicon is fabricated. The necessary sharp doping profile structure is created by means of MBE. Pronounced transistor action due to Esaki tunneling is demonstrated at room temperature. At a low supply voltage of -0.2 V a current gain of three magnitudes with saturation behaviour is achieved. MOS-gate, low supply voltage and exponential current increase make this device attractive for ULSI applications.
ISSN:	0040-6090 1879-2731
DOI:	10.1016/s0040-6090(00)00896-8