Structural and behavioral synthesis for testability techniques
In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit's behavioral description in C or VHDL as input. The outline of the system is as follows: (1)...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1994-06, Vol.13 (6), p.777-785 |
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Sprache: | eng |
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