High speed video compression testbed
This paper proposes a parallel processing architecture for a video compression testbed. Experiments for video coding algorithms can be performed and evaluated under this parallel processing architecture. The features of this testbed include (1) simulations of various hardware architectures, (2) test...
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| Veröffentlicht in: | IEEE transactions on consumer electronics 1994-08, Vol.40 (3), p.538-548 |
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| container_end_page | 548 |
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| container_issue | 3 |
| container_start_page | 538 |
| container_title | IEEE transactions on consumer electronics |
| container_volume | 40 |
| creator | Cheng, Ching-Min Wu, Chien-Hsing Pei, Soo-Chang Li, Hungwen Jeng, Bor-Shenn |
| description | This paper proposes a parallel processing architecture for a video compression testbed. Experiments for video coding algorithms can be performed and evaluated under this parallel processing architecture. The features of this testbed include (1) simulations of various hardware architectures, (2) test of specialized video compression circuits, and (3) testing ASICs for embedded applications as direct replacement of algorithms that have been certified. We illustrate its implementation, performance evaluation and benchmarking via JPEG/MPEG applications.< > |
| doi_str_mv | 10.1109/30.320839 |
| format | Article |
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| identifier | ISSN: 0098-3063 |
| ispartof | IEEE transactions on consumer electronics, 1994-08, Vol.40 (3), p.538-548 |
| issn | 0098-3063 1558-4127 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26423079 |
| source | IEEE Electronic Library (IEL) |
| subjects | Circuit testing Digital signal processors Hardware Parallel processing Signal processing algorithms System testing Telecommunication computing Transform coding Video compression Videoconference |
| title | High speed video compression testbed |
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