Failure-analysis-based test chip design for quick yield improvement
A new design approach for a test chip developed to shorten the debugging cycle time in fabrication is described. This approach meets the requirements for failure analysis as well as parametric and statistical analyses. Particular attention is devoted to accurate defect density estimation and to loca...
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| Veröffentlicht in: | Microelectronics and reliability 1996, Vol.36 (7), p.1063-1075 |
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| Hauptverfasser: | , |
| Format: | Artikel |
| Sprache: | eng |
| Online-Zugang: | Volltext |
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