Failure-analysis-based test chip design for quick yield improvement

Failure-analysis-based test chip design for quick yield improvement

A new design approach for a test chip developed to shorten the debugging cycle time in fabrication is described. This approach meets the requirements for failure analysis as well as parametric and statistical analyses. Particular attention is devoted to accurate defect density estimation and to loca...

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Veröffentlicht in:Microelectronics and reliability 1996, Vol.36 (7), p.1063-1075
Hauptverfasser: Hashimoto, Chisato, Nakajima, Shigeru
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container_issue 7
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container_title Microelectronics and reliability
container_volume 36
creator Hashimoto, Chisato
Nakajima, Shigeru
description A new design approach for a test chip developed to shorten the debugging cycle time in fabrication is described. This approach meets the requirements for failure analysis as well as parametric and statistical analyses. Particular attention is devoted to accurate defect density estimation and to locating individual defects. This is done by designing test structures suitable for both electrical measurements and failure analysis. A specially designed test chip, named YTEG, is used to evaluate 0.5-μm CMOS process technologies, and confirms the effectiveness of the chip.
doi_str_mv 10.1016/0026-2714(96)00030-3
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source ScienceDirect Journals (5 years ago - present)
title Failure-analysis-based test chip design for quick yield improvement
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