F-RISC/I: A 32 bit RISC processor implemented in GaAs HMESFET SBFL

F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. S...

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Bibliographische Detailangaben

Hauptverfasser:	Tien, C.K., Lewis, K., Philhower, R., Greub, H.J., McDonald, J.F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation Circuit synthesis Circuit testing Computational modeling Computer architecture Design automation Gallium arsenide Libraries Microprocessors Reduced instruction set computing
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