Advanced 'contact engineering' for submicron VLSI multilevel metallization
Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform...
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| Veröffentlicht in: | IEEE transactions on semiconductor manufacturing 1993-02, Vol.6 (1), p.22-27 |
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| container_title | IEEE transactions on semiconductor manufacturing |
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| creator | Young, K.K. Riley, P.E. Uesato, W. Whetten, T.J. Hu, H.K. Ray, G.W. Peng, S. Chiu, K.-Y. |
| description | Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth.< > |
| doi_str_mv | 10.1109/66.210655 |
| format | Article |
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The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth.< ></description><identifier>ISSN: 0894-6507</identifier><identifier>EISSN: 1558-2345</identifier><identifier>DOI: 10.1109/66.210655</identifier><identifier>CODEN: ITSMED</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Contact resistance ; Dielectrics ; Electronics ; Etching ; Exact sciences and technology ; Leakage current ; Metallization ; Microelectronic fabrication (materials and surfaces technology) ; Planarization ; Resists ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicides ; Silicon ; Very large scale integration</subject><ispartof>IEEE transactions on semiconductor manufacturing, 1993-02, Vol.6 (1), p.22-27</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c306t-668a665ac08b110aa04260ae6a2e994c23047a955fcf56034fc8703a134d65113</citedby><cites>FETCH-LOGICAL-c306t-668a665ac08b110aa04260ae6a2e994c23047a955fcf56034fc8703a134d65113</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/210655$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/210655$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4585156$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Young, K.K.</creatorcontrib><creatorcontrib>Riley, P.E.</creatorcontrib><creatorcontrib>Uesato, W.</creatorcontrib><creatorcontrib>Whetten, T.J.</creatorcontrib><creatorcontrib>Hu, H.K.</creatorcontrib><creatorcontrib>Ray, G.W.</creatorcontrib><creatorcontrib>Peng, S.</creatorcontrib><creatorcontrib>Chiu, K.-Y.</creatorcontrib><title>Advanced 'contact engineering' for submicron VLSI multilevel metallization</title><title>IEEE transactions on semiconductor manufacturing</title><addtitle>TSM</addtitle><description>Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth.< ></description><subject>Applied sciences</subject><subject>Contact resistance</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Etching</subject><subject>Exact sciences and technology</subject><subject>Leakage current</subject><subject>Metallization</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Planarization</subject><subject>Resists</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicides</subject><subject>Silicon</subject><subject>Very large scale integration</subject><issn>0894-6507</issn><issn>1558-2345</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNo9kDtPwzAUhS0EEqUwsDJlQFQMKXZs3yYjqngUVWLgsUa37k1l5CTFTirBr8coVac73O98OjqMXQo-FYIXdwDTTHDQ-oiNhNZ5mkmlj9mI54VKQfPZKTsL4YtzoVQxG7GX-_UOG0PrZGLapkPTJdRsbEPkbbOZJFXrk9Cvamt82ySfy7dFUveus4525JKaOnTO_mJn2-acnVToAl3s75h9PD68z5_T5evTYn6_TI3k0KUAOQJoNDxfxcqIXGXAkQAzKgplMsnVDAutK1Np4FJVJp9xiUKqNWgh5JjdDN6tb797Cl1Z22DIOWyo7UMZbTElZQRvBzB2D8FTVW69rdH_lIKX_2uVAOWwVmSv91IMBl3l4yg2HAJK51poiNjVgFkiOnz3jj8eu3AM</recordid><startdate>19930201</startdate><enddate>19930201</enddate><creator>Young, K.K.</creator><creator>Riley, P.E.</creator><creator>Uesato, W.</creator><creator>Whetten, T.J.</creator><creator>Hu, H.K.</creator><creator>Ray, G.W.</creator><creator>Peng, S.</creator><creator>Chiu, K.-Y.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19930201</creationdate><title>Advanced 'contact engineering' for submicron VLSI multilevel metallization</title><author>Young, K.K. ; Riley, P.E. ; Uesato, W. ; Whetten, T.J. ; Hu, H.K. ; Ray, G.W. ; Peng, S. ; Chiu, K.-Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-668a665ac08b110aa04260ae6a2e994c23047a955fcf56034fc8703a134d65113</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Contact resistance</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Etching</topic><topic>Exact sciences and technology</topic><topic>Leakage current</topic><topic>Metallization</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Planarization</topic><topic>Resists</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicides</topic><topic>Silicon</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Young, K.K.</creatorcontrib><creatorcontrib>Riley, P.E.</creatorcontrib><creatorcontrib>Uesato, W.</creatorcontrib><creatorcontrib>Whetten, T.J.</creatorcontrib><creatorcontrib>Hu, H.K.</creatorcontrib><creatorcontrib>Ray, G.W.</creatorcontrib><creatorcontrib>Peng, S.</creatorcontrib><creatorcontrib>Chiu, K.-Y.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on semiconductor manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Young, K.K.</au><au>Riley, P.E.</au><au>Uesato, W.</au><au>Whetten, T.J.</au><au>Hu, H.K.</au><au>Ray, G.W.</au><au>Peng, S.</au><au>Chiu, K.-Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Advanced 'contact engineering' for submicron VLSI multilevel metallization</atitle><jtitle>IEEE transactions on semiconductor manufacturing</jtitle><stitle>TSM</stitle><date>1993-02-01</date><risdate>1993</risdate><volume>6</volume><issue>1</issue><spage>22</spage><epage>27</epage><pages>22-27</pages><issn>0894-6507</issn><eissn>1558-2345</eissn><coden>ITSMED</coden><abstract>Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/66.210655</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0894-6507 |
| ispartof | IEEE transactions on semiconductor manufacturing, 1993-02, Vol.6 (1), p.22-27 |
| issn | 0894-6507 1558-2345 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26003433 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Contact resistance Dielectrics Electronics Etching Exact sciences and technology Leakage current Metallization Microelectronic fabrication (materials and surfaces technology) Planarization Resists Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicides Silicon Very large scale integration |
| title | Advanced 'contact engineering' for submicron VLSI multilevel metallization |
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