SH3: high code density, low power
Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding imp...
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| Veröffentlicht in: | IEEE MICRO 1995-12, Vol.15 (6), p.11-19 |
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| container_title | IEEE MICRO |
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| creator | Hasegawa, A. Kawasaki, I. Yamada, K. Yoshioka, S. Kawasaki, S. Biswas, P. |
| description | Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems. |
| doi_str_mv | 10.1109/40.476254 |
| format | Article |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0272-1732 |
| ispartof | IEEE MICRO, 1995-12, Vol.15 (6), p.11-19 |
| issn | 0272-1732 1937-4143 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_25976107 |
| source | IEEE Electronic Library (IEL) |
| subjects | Computer architecture Control system synthesis Counting circuits Energy consumption Energy management Microprocessors Multimedia systems Power system management Reduced instruction set computing |
| title | SH3: high code density, low power |
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