Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits

Advances in VLSI technologies have led to the implementation of very large and complex systems on a single chip. Current Computer Aided Design (CAD) tools are being pushed to their limits in order to keep up with increasing chip complexity. One of the main problems facing current CAD tools is the large amount of memory required when dealing with large systems. Most tools represent the circuit as a collection of primitives and shared information is duplicated. This paper discusses an approach for hierarchical switch-level simulation of digital circuits. The approach exploits the hierarchy to reduce the memory require ments of the simulation, allowing the simulation of circuits that are too large to simulate at the flat level. In addition, parts of the circuit can be replaced with automati cally generated software models, thus increasing the simulation speed without sacrificing accuracy. The approach has been implemented in a hierarchical switch-level simulator, CHAMP. The program allows for user-supplied behavioral models, assignable delays, and bidirectional signal flow inside circuit blocks that are repre sented as transistor networks as well as across the boundaries of higher level blocks.