Clock period minimization with wave pipelining

A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arriva...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 1993-04, Vol.12 (4), p.461-472
Hauptverfasser:	Joy, D.A., Ciesielski, M.J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Clocks Delay effects Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Feedback circuits Flip-flops Integrated circuits Interference constraints Logic circuits Minimization Pipeline processing Propagation delay Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Source separation
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