Architectural power analysis: The dual bit type method

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies chara...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 1995-06, Vol.3 (2), p.173-187
Hauptverfasser:	Landman, P.E., Rabaey, J.M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Circuits Delay estimation Energy consumption Power generation Power system modeling Process design Registers Semiconductor device modeling Very large scale integration
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