A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits
This paper describes a new scheduling algorithm for automatic synthesis of the control blocks of control-dominated circuits. The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG...
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| Veröffentlicht in: | Microprocessing and microprogramming 1995, Vol.41 (7), p.501-519 |
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| container_end_page | 519 |
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| container_issue | 7 |
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| container_title | Microprocessing and microprogramming |
| container_volume | 41 |
| creator | Huang, Shih-Hsu Hsu, Yu-Chin Oyang, Yen-Jen |
| description | This paper describes a new scheduling algorithm for automatic synthesis of the control blocks of control-dominated circuits. The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions. |
| doi_str_mv | 10.1016/0165-6074(95)00016-H |
| format | Article |
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The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.</description><identifier>ISSN: 0165-6074</identifier><identifier>DOI: 10.1016/0165-6074(95)00016-H</identifier><identifier>CODEN: MMICDT</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Algorithmics. Computability. Computer arithmetics ; Applied sciences ; Computer science; control theory; systems ; Control system synthesis ; Control theory. Systems ; Control-dominated circuit synthesis ; Electronics ; Exact sciences and technology ; Finite state machines ; High-level synthesis ; Integrated circuits ; Operation chaining ; Scheduling ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.</description><subject>Algorithmics. Computability. Computer arithmetics</subject><subject>Applied sciences</subject><subject>Computer science; control theory; systems</subject><subject>Control system synthesis</subject><subject>Control theory. Systems</subject><subject>Control-dominated circuit synthesis</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Finite state machines</subject><subject>High-level synthesis</subject><subject>Integrated circuits</subject><subject>Operation chaining</subject><subject>Scheduling</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Computability. Computer arithmetics</topic><topic>Applied sciences</topic><topic>Computer science; control theory; systems</topic><topic>Control system synthesis</topic><topic>Control theory. Systems</topic><topic>Control-dominated circuit synthesis</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Finite state machines</topic><topic>High-level synthesis</topic><topic>Integrated circuits</topic><topic>Operation chaining</topic><topic>Scheduling</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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| ispartof | Microprocessing and microprogramming, 1995, Vol.41 (7), p.501-519 |
| issn | 0165-6074 |
| language | eng |
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| source | Alma/SFX Local Collection |
| subjects | Algorithmics. Computability. Computer arithmetics Applied sciences Computer science control theory systems Control system synthesis Control theory. Systems Control-dominated circuit synthesis Electronics Exact sciences and technology Finite state machines High-level synthesis Integrated circuits Operation chaining Scheduling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Theoretical computing |
| title | A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits |
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