Reconfigurable SIMD massively parallel computers
This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph...
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Veröffentlicht in: | Proceedings of the IEEE 1991-04, Vol.79 (4), p.429-443 |
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container_title | Proceedings of the IEEE |
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creator | Li, H. Stout, Q.F. |
description | This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed.< > |
doi_str_mv | 10.1109/5.92038 |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_25394357</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>92038</ieee_id><sourcerecordid>25394357</sourcerecordid><originalsourceid>FETCH-LOGICAL-c302t-fb62e2df708bdf33f76e04e6cbbf309ee7fe96c1e6c3a0da450001a8351da2d3</originalsourceid><addsrcrecordid>eNpF0E1LxDAQBuAgCq6rePbWi3rqOkk2bXOU9WthRdC9h2k6kUq6rclW2H9vtYueBmYeXoaXsXMOM85B36iZFiCLAzbhShWpECo7ZBMAXqRacH3MTmL8AACpMjlh8Eq23bj6vQ9Yekrels93SYMx1l_kd0mHAb0nn9i26fothXjKjhz6SGf7OWXrh_v14ildvTwuF7er1EoQ29SVmSBRuRyKsnJSujwjmFNmy9JJ0ES5I51ZPmwkQoVzNbzEsZCKVygqOWVXY2wX2s-e4tY0dbTkPW6o7aMRSuq5VPkAr0doQxtjIGe6UDcYdoaD-SnEKPNbyCAv95EYLXoXcGPr-M91wXPO-eAuRlcT0d95zPgG6PBnYw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>25394357</pqid></control><display><type>article</type><title>Reconfigurable SIMD massively parallel computers</title><source>IEEE Electronic Library (IEL)</source><creator>Li, H. ; Stout, Q.F.</creator><creatorcontrib>Li, H. ; Stout, Q.F.</creatorcontrib><description>This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed.< ></description><identifier>ISSN: 0018-9219</identifier><identifier>EISSN: 1558-2256</identifier><identifier>DOI: 10.1109/5.92038</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Computer architecture ; Computer networks ; Computers, microcomputers ; Concurrent computing ; Degradation ; Electronics ; Embedded computing ; Exact sciences and technology ; Fault tolerance ; Hardware ; Multiprocessor interconnection networks ; Network topology ; Parallel architectures ; Parallel processing</subject><ispartof>Proceedings of the IEEE, 1991-04, Vol.79 (4), p.429-443</ispartof><rights>1991 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c302t-fb62e2df708bdf33f76e04e6cbbf309ee7fe96c1e6c3a0da450001a8351da2d3</citedby><cites>FETCH-LOGICAL-c302t-fb62e2df708bdf33f76e04e6cbbf309ee7fe96c1e6c3a0da450001a8351da2d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/92038$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/92038$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=19817111$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Li, H.</creatorcontrib><creatorcontrib>Stout, Q.F.</creatorcontrib><title>Reconfigurable SIMD massively parallel computers</title><title>Proceedings of the IEEE</title><addtitle>JPROC</addtitle><description>This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed.< ></description><subject>Applied sciences</subject><subject>Computer architecture</subject><subject>Computer networks</subject><subject>Computers, microcomputers</subject><subject>Concurrent computing</subject><subject>Degradation</subject><subject>Electronics</subject><subject>Embedded computing</subject><subject>Exact sciences and technology</subject><subject>Fault tolerance</subject><subject>Hardware</subject><subject>Multiprocessor interconnection networks</subject><subject>Network topology</subject><subject>Parallel architectures</subject><subject>Parallel processing</subject><issn>0018-9219</issn><issn>1558-2256</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1991</creationdate><recordtype>article</recordtype><recordid>eNpF0E1LxDAQBuAgCq6rePbWi3rqOkk2bXOU9WthRdC9h2k6kUq6rclW2H9vtYueBmYeXoaXsXMOM85B36iZFiCLAzbhShWpECo7ZBMAXqRacH3MTmL8AACpMjlh8Eq23bj6vQ9Yekrels93SYMx1l_kd0mHAb0nn9i26fothXjKjhz6SGf7OWXrh_v14ildvTwuF7er1EoQ29SVmSBRuRyKsnJSujwjmFNmy9JJ0ES5I51ZPmwkQoVzNbzEsZCKVygqOWVXY2wX2s-e4tY0dbTkPW6o7aMRSuq5VPkAr0doQxtjIGe6UDcYdoaD-SnEKPNbyCAv95EYLXoXcGPr-M91wXPO-eAuRlcT0d95zPgG6PBnYw</recordid><startdate>19910401</startdate><enddate>19910401</enddate><creator>Li, H.</creator><creator>Stout, Q.F.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19910401</creationdate><title>Reconfigurable SIMD massively parallel computers</title><author>Li, H. ; Stout, Q.F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c302t-fb62e2df708bdf33f76e04e6cbbf309ee7fe96c1e6c3a0da450001a8351da2d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Applied sciences</topic><topic>Computer architecture</topic><topic>Computer networks</topic><topic>Computers, microcomputers</topic><topic>Concurrent computing</topic><topic>Degradation</topic><topic>Electronics</topic><topic>Embedded computing</topic><topic>Exact sciences and technology</topic><topic>Fault tolerance</topic><topic>Hardware</topic><topic>Multiprocessor interconnection networks</topic><topic>Network topology</topic><topic>Parallel architectures</topic><topic>Parallel processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Li, H.</creatorcontrib><creatorcontrib>Stout, Q.F.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Proceedings of the IEEE</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, H.</au><au>Stout, Q.F.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Reconfigurable SIMD massively parallel computers</atitle><jtitle>Proceedings of the IEEE</jtitle><stitle>JPROC</stitle><date>1991-04-01</date><risdate>1991</risdate><volume>79</volume><issue>4</issue><spage>429</spage><epage>443</epage><pages>429-443</pages><issn>0018-9219</issn><eissn>1558-2256</eissn><coden>IEEPAD</coden><abstract>This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/5.92038</doi><tpages>15</tpages></addata></record> |
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subjects | Applied sciences Computer architecture Computer networks Computers, microcomputers Concurrent computing Degradation Electronics Embedded computing Exact sciences and technology Fault tolerance Hardware Multiprocessor interconnection networks Network topology Parallel architectures Parallel processing |
title | Reconfigurable SIMD massively parallel computers |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T18%3A07%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Reconfigurable%20SIMD%20massively%20parallel%20computers&rft.jtitle=Proceedings%20of%20the%20IEEE&rft.au=Li,%20H.&rft.date=1991-04-01&rft.volume=79&rft.issue=4&rft.spage=429&rft.epage=443&rft.pages=429-443&rft.issn=0018-9219&rft.eissn=1558-2256&rft.coden=IEEPAD&rft_id=info:doi/10.1109/5.92038&rft_dat=%3Cproquest_RIE%3E25394357%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=25394357&rft_id=info:pmid/&rft_ieee_id=92038&rfr_iscdi=true |