Laser simulation of single-event upset in a p-well CMOS counter
A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly depen...
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| Veröffentlicht in: | IEEE transactions on nuclear science 1989-02, Vol.36 (1), p.1330-1332 |
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| container_end_page | 1332 |
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| container_title | IEEE transactions on nuclear science |
| container_volume | 36 |
| creator | Mazer, J.A. Kang, K. Buchner, S. |
| description | A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.< > |
| doi_str_mv | 10.1109/TNS.1989.574133 |
| format | Article |
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It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.< ></description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.1989.574133</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit simulation ; CMOS logic circuits ; CMOS memory circuits ; Counting circuits ; Design. Technologies. Operation analysis. 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It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.< ></description><subject>Applied sciences</subject><subject>Circuit simulation</subject><subject>CMOS logic circuits</subject><subject>CMOS memory circuits</subject><subject>Counting circuits</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Lighting</subject><subject>Logic circuits</subject><subject>Read-write memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Single event upset</subject><subject>SRAM chips</subject><subject>Voltage</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1989</creationdate><recordtype>article</recordtype><recordid>eNqFkD1PwzAQhi0EEqUwIzF5gS2tzx-JMyFU8SUVOrTMluueUVCaBDsB8e9JSQUj0-l0z_vq9BByDmwCwPLp6nk5gVznE5VJEOKAjEApnYDK9CEZMQY6yWWeH5OTGN_6VSqmRuR6biMGGottV9q2qCta-36rXktM8AOrlnZNxJYWFbW0ST6xLOnsabGkru6qFsMpOfK2jHi2n2Pycne7mj0k88X94-xmnjiheJtIZdOMKYtgpdhokMx6pdbKpWg53yDLlAPt14wj42nmWbpWwCCz3krJPBdjcjX0NqF-7zC2ZltE139jK6y7aLgWwAQX_4OKayZy6MHpALpQxxjQmyYUWxu-DDCzM2p6o2Zn1AxG-8TlvtpGZ0sfbOWK-Bfr9Wr103wxcAUi_p73Jd_foXzE</recordid><startdate>19890201</startdate><enddate>19890201</enddate><creator>Mazer, J.A.</creator><creator>Kang, K.</creator><creator>Buchner, S.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7U5</scope></search><sort><creationdate>19890201</creationdate><title>Laser simulation of single-event upset in a p-well CMOS counter</title><author>Mazer, J.A. ; Kang, K. ; Buchner, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c352t-45a6705ae1a43d8140af55b5c6ea22de075c18fb02e0267f06b51017afa440f23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1989</creationdate><topic>Applied sciences</topic><topic>Circuit simulation</topic><topic>CMOS logic circuits</topic><topic>CMOS memory circuits</topic><topic>Counting circuits</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Lighting</topic><topic>Logic circuits</topic><topic>Read-write memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Single event upset</topic><topic>SRAM chips</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mazer, J.A.</creatorcontrib><creatorcontrib>Kang, K.</creatorcontrib><creatorcontrib>Buchner, S.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on nuclear science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mazer, J.A.</au><au>Kang, K.</au><au>Buchner, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Laser simulation of single-event upset in a p-well CMOS counter</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>1989-02-01</date><risdate>1989</risdate><volume>36</volume><issue>1</issue><spage>1330</spage><epage>1332</epage><pages>1330-1332</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TNS.1989.574133</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0018-9499 |
| ispartof | IEEE transactions on nuclear science, 1989-02, Vol.36 (1), p.1330-1332 |
| issn | 0018-9499 1558-1578 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_25280391 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit simulation CMOS logic circuits CMOS memory circuits Counting circuits Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Lighting Logic circuits Read-write memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Single event upset SRAM chips Voltage |
| title | Laser simulation of single-event upset in a p-well CMOS counter |
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