Constrained via minimization for three-layer routing
The constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. This problem has been shown to be NP-complete 15. In this paper, this pr...
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| Veröffentlicht in: | Computer aided design 1989-07, Vol.21 (6), p.346-354 |
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| container_title | Computer aided design |
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| creator | Chang, K.E. Jyu, H.F. Feng, W.S. |
| description | The constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. This problem has been shown to be NP-complete
15. In this paper, this problem is first transformed to the contractibility problem of a three-colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of vias can be reduced by about 30%. |
| doi_str_mv | 10.1016/0010-4485(89)90001-8 |
| format | Article |
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15. In this paper, this problem is first transformed to the contractibility problem of a three-colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of vias can be reduced by about 30%.</description><subject>Applied sciences</subject><subject>computer-aided design</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>graph contractibility</subject><subject>Integrated circuits</subject><subject>layer assignment</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>via minimization</subject><subject>VLSI design</subject><issn>0010-4485</issn><issn>1879-2685</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1989</creationdate><recordtype>article</recordtype><recordid>eNp9kEtLxDAUhYMoOI7-AxddiOiimvSZbAQpvmDAja7DbXKjkTYZk87A-OttnWGWri4HvnMu5xByzugNo6y6pZTRtCh4ecXFtaCjTPkBmTFeizSreHlIZnvkmJzE-DUyGcvFjBSNd3EIYB3qZG0h6a2zvf2BwXqXGB-S4TMgph1sMCTBrwbrPk7JkYEu4tnuzsn748Nb85wuXp9emvtFqrJaDGmbc9Oqsi5aZbioBVCat8xwrbECjgxNTUuuM2ryFlFVkOdty3VNQUMpEPI5udzmLoP_XmEcZG-jwq4Dh34VZVayigrKR7DYgir4GAMauQy2h7CRjMppIjn1l1N_yYX8m0hOtotdPkQFnQnglI17b1VWgtVixO62GI5d1xaDjMqiU6htQDVI7e3_f34BtW96_g</recordid><startdate>19890701</startdate><enddate>19890701</enddate><creator>Chang, K.E.</creator><creator>Jyu, H.F.</creator><creator>Feng, W.S.</creator><general>Elsevier Ltd</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>19890701</creationdate><title>Constrained via minimization for three-layer routing</title><author>Chang, K.E. ; Jyu, H.F. ; Feng, W.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c279t-b38fbc574bcf8979a003b1f8dde6a8e1ef7058d20f3beec6a33bb8d70ada59ea3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1989</creationdate><topic>Applied sciences</topic><topic>computer-aided design</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>graph contractibility</topic><topic>Integrated circuits</topic><topic>layer assignment</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>via minimization</topic><topic>VLSI design</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chang, K.E.</creatorcontrib><creatorcontrib>Jyu, H.F.</creatorcontrib><creatorcontrib>Feng, W.S.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>Computer aided design</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chang, K.E.</au><au>Jyu, H.F.</au><au>Feng, W.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Constrained via minimization for three-layer routing</atitle><jtitle>Computer aided design</jtitle><date>1989-07-01</date><risdate>1989</risdate><volume>21</volume><issue>6</issue><spage>346</spage><epage>354</epage><pages>346-354</pages><issn>0010-4485</issn><eissn>1879-2685</eissn><coden>CAIDA5</coden><abstract>The constrained via minimization problem for VLSI three-layer routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. This problem has been shown to be NP-complete
15. In this paper, this problem is first transformed to the contractibility problem of a three-colourable graph, then an heuristic algorithm is proposed on the basis of the graph contractability model. From experimental results, the algorithm proves faster and more efficient at generating very good results. For a typical case, the number of vias can be reduced by about 30%.</abstract><cop>Oxford</cop><pub>Elsevier Ltd</pub><doi>10.1016/0010-4485(89)90001-8</doi><tpages>9</tpages></addata></record> |
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| ispartof | Computer aided design, 1989-07, Vol.21 (6), p.346-354 |
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| source | Access via ScienceDirect (Elsevier) |
| subjects | Applied sciences computer-aided design Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology graph contractibility Integrated circuits layer assignment Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices via minimization VLSI design |
| title | Constrained via minimization for three-layer routing |
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