Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth
Three-dimensionally integrated silicon-on-insulator MOS transistors built employing localized silicon epitaxy are discussed. Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the bu...
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| Veröffentlicht in: | IEEE transactions on electron devices 1990-06, Vol.37 (6), p.1452-1461 |
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| container_end_page | 1461 |
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| container_issue | 6 |
| container_start_page | 1452 |
| container_title | IEEE transactions on electron devices |
| container_volume | 37 |
| creator | Zingg, R.P. Friedrich, J.A. Neudeck, G.W. Hofflinger, B. |
| description | Three-dimensionally integrated silicon-on-insulator MOS transistors built employing localized silicon epitaxy are discussed. Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated.< > |
| doi_str_mv | 10.1109/16.106240 |
| format | Article |
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Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated.< ></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.106240</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; CMOS technology ; Crystalline materials ; Design. Technologies. Operation analysis. Testing ; Electronics ; Epitaxial growth ; Exact sciences and technology ; Insulation ; Integrated circuits ; Isolation technology ; MOS devices ; MOSFETs ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated.< ></description><subject>Applied sciences</subject><subject>CMOS technology</subject><subject>Crystalline materials</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Epitaxial growth</subject><subject>Exact sciences and technology</subject><subject>Insulation</subject><subject>Integrated circuits</subject><subject>Isolation technology</subject><subject>MOS devices</subject><subject>MOSFETs</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon on insulator technology</subject><subject>Ultra large scale integration</subject><subject>Very large scale integration</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNqFkb1PwzAQxS0EEqUwsDJlAYkhxY4_Eo-o4ksq6tAyR7ZzoYY0LnYKlL8eQyrB1ul0d7_3hvcQOiV4RAiWV0SMCBYZw3toQDjPUymY2EcDjEmRSlrQQ3QUwktcBWPZAM3mCw-QVnYJbbCuVU0SOmVeoUoep7Ok8yqeQ-d8SPQmaZxRjf2Kz2Aba1ybwMp26tNGmXsH_-zdR7c4Rge1agKcbOcQPd3ezMf36WR69zC-nqSGctylVAA1umCZ0BJ0hXMqC6LqLFcajNGa6IpoWWgWD7WqiBEaC0mFynOmc07pEF30vivv3tYQunJpg4GmUS24dSgziUWecbkbLASXDLPdIMe8yDCP4GUPGu9C8FCXK2-Xym9KgsufIkoiyr6IyJ5vTVWI8dUxUmPDn0BSGkMoInfWcxYA_vn9mnwDn-GQ6A</recordid><startdate>19900601</startdate><enddate>19900601</enddate><creator>Zingg, R.P.</creator><creator>Friedrich, J.A.</creator><creator>Neudeck, G.W.</creator><creator>Hofflinger, B.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><scope>7SP</scope><scope>7U5</scope></search><sort><creationdate>19900601</creationdate><title>Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth</title><author>Zingg, R.P. ; Friedrich, J.A. ; Neudeck, G.W. ; Hofflinger, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c350t-36e3cb8426b9ebd073981af27abeccbb1bd1b98b47abfad1c6b06936a774b7533</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Applied sciences</topic><topic>CMOS technology</topic><topic>Crystalline materials</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Epitaxial growth</topic><topic>Exact sciences and technology</topic><topic>Insulation</topic><topic>Integrated circuits</topic><topic>Isolation technology</topic><topic>MOS devices</topic><topic>MOSFETs</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon on insulator technology</topic><topic>Ultra large scale integration</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zingg, R.P.</creatorcontrib><creatorcontrib>Friedrich, J.A.</creatorcontrib><creatorcontrib>Neudeck, G.W.</creatorcontrib><creatorcontrib>Hofflinger, B.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zingg, R.P.</au><au>Friedrich, J.A.</au><au>Neudeck, G.W.</au><au>Hofflinger, B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1990-06-01</date><risdate>1990</risdate><volume>37</volume><issue>6</issue><spage>1452</spage><epage>1461</epage><pages>1452-1461</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Three-dimensionally integrated silicon-on-insulator MOS transistors built employing localized silicon epitaxy are discussed. Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/16.106240</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1990-06, Vol.37 (6), p.1452-1461 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_25058205 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences CMOS technology Crystalline materials Design. Technologies. Operation analysis. Testing Electronics Epitaxial growth Exact sciences and technology Insulation Integrated circuits Isolation technology MOS devices MOSFETs Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon on insulator technology Ultra large scale integration Very large scale integration |
| title | Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth |
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