Soft-error-immune switched-load-resistor memory cell
A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges g...
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| Veröffentlicht in: | IEEE transactions on electron devices 1988-12, Vol.35 (12), p.2094-2100 |
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| container_end_page | 2100 |
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| container_issue | 12 |
| container_start_page | 2094 |
| container_title | IEEE transactions on electron devices |
| container_volume | 35 |
| creator | Homma, N. Nakamura, T. Hayashida, T. Matsumoto, M. Nakazato, K. Onai, T. Tamaki, Y. Namba, M. Sagara, K. Ikeda, K. |
| description | A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p/sup -/-substrate are completely shielded by n/sup +/-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10/sup 5/ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell.< > |
| doi_str_mv | 10.1109/16.8782 |
| format | Article |
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The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p/sup -/-substrate are completely shielded by n/sup +/-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10/sup 5/ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell.< ></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.8782</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Active noise reduction ; Applied sciences ; Capacitance ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Electrons ; Exact sciences and technology ; Noise generators ; Noise reduction ; Random access memory ; Read-write memory ; Schottky diodes ; Silicon ; Voltage</subject><ispartof>IEEE transactions on electron devices, 1988-12, Vol.35 (12), p.2094-2100</ispartof><rights>1990 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c300t-5ade37dd5d550b682ad2ce90a97d171b52c4bf4f6f422cd6e1e1eba10bd6fa043</citedby><cites>FETCH-LOGICAL-c300t-5ade37dd5d550b682ad2ce90a97d171b52c4bf4f6f422cd6e1e1eba10bd6fa043</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8782$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8782$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=6828697$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Homma, N.</creatorcontrib><creatorcontrib>Nakamura, T.</creatorcontrib><creatorcontrib>Hayashida, T.</creatorcontrib><creatorcontrib>Matsumoto, M.</creatorcontrib><creatorcontrib>Nakazato, K.</creatorcontrib><creatorcontrib>Onai, T.</creatorcontrib><creatorcontrib>Tamaki, Y.</creatorcontrib><creatorcontrib>Namba, M.</creatorcontrib><creatorcontrib>Sagara, K.</creatorcontrib><creatorcontrib>Ikeda, K.</creatorcontrib><title>Soft-error-immune switched-load-resistor memory cell</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p/sup -/-substrate are completely shielded by n/sup +/-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10/sup 5/ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell.< ></description><subject>Active noise reduction</subject><subject>Applied sciences</subject><subject>Capacitance</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Electrons</subject><subject>Exact sciences and technology</subject><subject>Noise generators</subject><subject>Noise reduction</subject><subject>Random access memory</subject><subject>Read-write memory</subject><subject>Schottky diodes</subject><subject>Silicon</subject><subject>Voltage</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1988</creationdate><recordtype>article</recordtype><recordid>eNo9kM1LAzEQxYMoWKt49diD6Ck1ySbZ3aOU-gEFD-o5ZJMJRnabmtki_e_dtaXMYRjmx-O9R8g1Z3POWf3A9bwqK3FCJlypktZa6lMyYYxXtC6q4pxcIH4Pp5ZSTIh8T6GnkHPKNHbddg0z_I29-wJP22Q9zYAR-5RnHXQp72YO2vaSnAXbIlwd9pR8Pi0_Fi909fb8unhcUVcw1lNlPRSl98orxRpdCeuFg5rZuvS85I0STjZBBh2kEM5r4MM0lrPG62CZLKbkbq-7yelnC9ibLuJowK4hbdEINcZQYgDv96DLCTFDMJscO5t3hjMztmK4NmMrA3l7kLTobBuyXbuIR3wwWem6HLCbPRYB4Pj9V_gDwMVpLw</recordid><startdate>19881201</startdate><enddate>19881201</enddate><creator>Homma, N.</creator><creator>Nakamura, T.</creator><creator>Hayashida, T.</creator><creator>Matsumoto, M.</creator><creator>Nakazato, K.</creator><creator>Onai, T.</creator><creator>Tamaki, Y.</creator><creator>Namba, M.</creator><creator>Sagara, K.</creator><creator>Ikeda, K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19881201</creationdate><title>Soft-error-immune switched-load-resistor memory cell</title><author>Homma, N. ; Nakamura, T. ; Hayashida, T. ; Matsumoto, M. ; Nakazato, K. ; Onai, T. ; Tamaki, Y. ; Namba, M. ; Sagara, K. ; Ikeda, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c300t-5ade37dd5d550b682ad2ce90a97d171b52c4bf4f6f422cd6e1e1eba10bd6fa043</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Active noise reduction</topic><topic>Applied sciences</topic><topic>Capacitance</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Electrons</topic><topic>Exact sciences and technology</topic><topic>Noise generators</topic><topic>Noise reduction</topic><topic>Random access memory</topic><topic>Read-write memory</topic><topic>Schottky diodes</topic><topic>Silicon</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Homma, N.</creatorcontrib><creatorcontrib>Nakamura, T.</creatorcontrib><creatorcontrib>Hayashida, T.</creatorcontrib><creatorcontrib>Matsumoto, M.</creatorcontrib><creatorcontrib>Nakazato, K.</creatorcontrib><creatorcontrib>Onai, T.</creatorcontrib><creatorcontrib>Tamaki, Y.</creatorcontrib><creatorcontrib>Namba, M.</creatorcontrib><creatorcontrib>Sagara, K.</creatorcontrib><creatorcontrib>Ikeda, K.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Homma, N.</au><au>Nakamura, T.</au><au>Hayashida, T.</au><au>Matsumoto, M.</au><au>Nakazato, K.</au><au>Onai, T.</au><au>Tamaki, Y.</au><au>Namba, M.</au><au>Sagara, K.</au><au>Ikeda, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Soft-error-immune switched-load-resistor memory cell</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1988-12-01</date><risdate>1988</risdate><volume>35</volume><issue>12</issue><spage>2094</spage><epage>2100</epage><pages>2094-2100</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p/sup -/-substrate are completely shielded by n/sup +/-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10/sup 5/ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/16.8782</doi><tpages>7</tpages></addata></record> |
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| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1988-12, Vol.35 (12), p.2094-2100 |
| issn | 0018-9383 1557-9646 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Active noise reduction Applied sciences Capacitance Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Electrons Exact sciences and technology Noise generators Noise reduction Random access memory Read-write memory Schottky diodes Silicon Voltage |
| title | Soft-error-immune switched-load-resistor memory cell |
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